公开(公告)号：US11189700B2

公开(公告)日：2021-11-30

申请号：US15773549

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Van H. Le ,  Rafael Rios ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Marko Radosavljevic

IPC: H01L29/24 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L27/092 ,  H01L29/417 ,  H01L29/775 ,  H01L21/443 ,  H01L21/768 ,  H01L29/04 ,  H01L29/45 ,  H01L21/02

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and an IGZO fin formed above the substrate. Embodiments may include a source contact and a drain contact that are formed adjacent to more than one surface of the IGZO fin. Additionally, embodiments may include a gate electrode formed between the source contact and the drain contact. The gate electrode may be separated from the IGZO layer by a gate dielectric. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US11145739B2

公开(公告)日：2021-10-12

申请号：US16075953

申请日：2016-03-04

Applicant: Intel Corporation

Inventor： Gilbert W. Dewey ,  Rafael Rios ,  Van H. Le ,  Jack T. Kavalieros

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/092 ,  H01L21/465 ,  H01L29/267

Abstract: FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

公开(公告)号：US10964701B2

公开(公告)日：2021-03-30

申请号：US16480948

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Van H. Le ,  Gilbert William Dewey ,  Rafael Rios ,  Jack T. Kavalieros ,  Yih Wang ,  Shriram Shivaraman

IPC: H01L27/108 ,  G11C11/401 ,  G11C11/404 ,  G11C11/408 ,  G11C11/4096 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L27/13 ,  H01L49/02 ,  H01L29/22 ,  H01L29/24 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/3105

Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.

公开(公告)号：US10727138B2

公开(公告)日：2020-07-28

申请号：US16094452

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Van H. Le ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Rafael Rios ,  Gilbert Dewey

IPC: H01L21/84 ,  H01L29/423 ,  H01L29/417 ,  H01L21/822 ,  H01L29/41 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/08 ,  H01L27/06 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12 ,  H01L27/092 ,  H01L21/02 ,  H01L23/532

Abstract: A monocrystalline semiconductor layer is formed on a conductive layer on an insulating layer on a substrate. The conductive layer is a part of an interconnect layer. The monocrystalline semiconductor layer extends laterally on the insulating layer. Other embodiments may be described and/or claimed.

公开(公告)号：US10659046B2

公开(公告)日：2020-05-19

申请号：US15755021

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Rafael Rios ,  Van Le ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H03K19/00 ,  G06F30/30 ,  G06F30/39 ,  G06F1/3203 ,  H01L27/02 ,  H03K19/094

Abstract: A power gating switch is described at a local cell level of an integrated circuit die. In one example a plurality of logic cells have a data input line and a data output line and a power supply input to receive power to drive circuits of the logic cell. A power switch for each logic cell is coupled between a power supply and the power supply input of the respective logic cell to control power being connected from the power supply to the respective logic cell.

公开(公告)号：US10586868B2

公开(公告)日：2020-03-10

申请号：US15024714

申请日：2013-12-19

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Rafael Rios ,  Fahmida Ferdousi ,  Kelin J. Kuhn

IPC: H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/10 ,  H01L29/786

Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.

公开(公告)号：US10535770B2

公开(公告)日：2020-01-14

申请号：US15505558

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Rafael Rios ,  Kelin J. Kuhn ,  Ian A. Young ,  Justin R. Weber

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  B82Y10/00 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/66

Abstract: Described is a TFET comprising: a nanowire having doped regions for forming source and drain regions, and an un-doped region for coupling to a gate region; and a first termination material formed over the nanowire; and a second termination material formed over a section of the nanowire overlapping the gate and source regions. Described is another TFET comprising: a first section of a nanowire having doped regions for forming source and drain regions, and an undoped region for coupling to a gate region; a second section of the nanowire extending orthogonal to the first section, the second section formed next to the gate and source regions; and a termination material formed over the first and second sections of the nanowire.

公开(公告)号：US20190214466A1

公开(公告)日：2019-07-11

申请号：US16325420

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Van H. Le ,  Ashish Agrawal ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Seung Hoon Sung ,  Rafael Rios ,  Gilbert Dewey

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/267 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L21/02 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/768 ,  H01L29/165 ,  H01L29/267 ,  H01L29/32 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: An embodiment includes a device comprising: a substrate; a dielectric layer on the substrate and including a trench; a first portion of the trench including a first material that comprises at least one of a group III-V material and a group IV material; and a second portion of the trench, located between the first portion and the substrate, which includes a second material and an upper region and a lower region; wherein: (a)(i) the second material in the upper region has fewer defects than the second material in the lower region, and (a)(ii) the first material is strained. Other embodiments are described herein.

公开(公告)号：US09825130B2

公开(公告)日：2017-11-21

申请号：US13996845

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Kelin Kuhn ,  Rafael Rios ,  Mark Armstrong

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A nanowire device of the present description may include a highly doped underlayer formed between at least one nanowire transistor and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer may reduce or substantially eliminate leakage and high gate capacitance which can occur at a bottom portion of a gate structure of the nanowire transistors. As the formation of the highly doped underlayer may result in gate inducted drain leakage at an interface between source structures and drain structures of the nanowire transistors, a thin layer of undoped or low doped material may be formed between the highly doped underlayer and the nanowire transistors.

公开(公告)号：US11456372B2

公开(公告)日：2022-09-27

申请号：US15576251

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Gopinath Bhimarasetti ,  Rafael Rios ,  Jack T. Kavalieros ,  Tahir Ghani ,  Anand S. Murthy ,  Rishabh Mehandru

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L21/02 ,  H01L27/088 ,  H01L23/498 ,  H01L29/08

Abstract: A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.