中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

321 records (took 0.128 seconds)

    GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES INCLUDING VARACTORS
    34.
    发明申请
    GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES INCLUDING VARACTORS 有权

    公开(公告)号：US20210305436A1

    公开(公告)日：2021-09-30

    申请号：US16830112

    申请日：2020-03-25

    Applicant: Intel Corporation

    Inventor： Ayan KAR ,  Saurabh MORARKA ,  Carlos NIEVA-LOZANO ,  Kalyan KOLLURU ,  Biswajeet GUHA ,  Chung-Hsun LIN ,  Brian GREENE ,  Tahir GHANI

    IPC: H01L29/93 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

    Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

    SELF-ALIGNED GATE EDGE TRIGATE AND FINFET DEVICES
    36.
    发明申请
    SELF-ALIGNED GATE EDGE TRIGATE AND FINFET DEVICES 有权

    公开(公告)号：US20210249411A1

    公开(公告)日：2021-08-12

    申请号：US17242021

    申请日：2021-04-27

    Applicant: Intel Corporation

    Inventor： Szuya S. LIAO ,  Biswajeet GUHA ,  Tahir GHANI ,  Christopher N. KENYON ,  Leonard P. GULER

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535

    Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.

    INTEGRATED CIRCUIT STRUCTURES WITH SOURCE OR DRAIN DOPANT DIFFUSION BLOCKING LAYERS
    39.
    发明申请
    INTEGRATED CIRCUIT STRUCTURES WITH SOURCE OR DRAIN DOPANT DIFFUSION BLOCKING LAYERS 审中-公开

    公开(公告)号：US20200219975A1

    公开(公告)日：2020-07-09

    申请号：US16238858

    申请日：2019-01-03

    Applicant: Intel Corporation

    Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Anupama BOWONDER ,  Aaron BUDREVICH ,  Tahir GHANI

    IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

    Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.

    GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SELF-ALIGNED SOURCE OR DRAIN UNDERCUT FOR VARIED WIDTHS
    40.
    发明申请
    GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SELF-ALIGNED SOURCE OR DRAIN UNDERCUT FOR VARIED WIDTHS 审中-公开

    公开(公告)号：US20200091145A1

    公开(公告)日：2020-03-19

    申请号：US16134824

    申请日：2018-09-18

    Applicant: Intel Corporation

    Inventor： Biswajeet GUHA ,  Jun Sung KANG ,  Bruce BEATTIE ,  Stephen M. CEA ,  Tahir GHANI

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234

    Abstract: Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths are described. In an example, a structure includes first and second vertical arrangements of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stack portions are over the first and second vertical arrangements of nanowires, respectively. First embedded epitaxial source or drain regions are at ends of the first vertical arrangement of nanowires and extend beneath dielectric sidewalls spacers of the first gate stack portion by a first distance. Second embedded epitaxial source or drain regions are at ends of the second vertical arrangement of nanowires and extend beneath the dielectric sidewalls spacers of the second gate stack portion by a second distance substantially the same as the first distance.

Patent Agency Ranking