公开(公告)号：US20210049102A1

公开(公告)日：2021-02-18

申请号：US16834845

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US10782729B2

公开(公告)日：2020-09-22

申请号：US15827604

申请日：2017-11-30

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Vedaraman Geetha ,  Don C. Soltis, Jr. ,  Samuel Strom ,  Jason Crop

IPC: G06F1/14 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3234 ,  G06F9/22

Abstract: In an embodiment, a processor for clock signal modulation includes a clock source to generate a global clock signal, at least one processor component, a counter, and a circuit. The circuit is to: adjust the counter based on a level of activity of the at least one processor component; modulate, based on a value of the counter, the global clock signal to generate a modulated clock signal; and provide the modulated clock signal to the at least one processor component. Other embodiments are described and claimed.

公开(公告)号：US10514990B2

公开(公告)日：2019-12-24

申请号：US15823313

申请日：2017-11-27

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Swadesh Choudhary ,  Rahul Pal ,  Vedaraman Geetha

IPC: G06F11/20 ,  G06F11/18 ,  G06F11/14 ,  G06F9/38

Abstract: Operational faults, including transient faults, are detected within computing hardware for mission-critical applications. Operational requests received from a requestor node are to be processed by shared agents to produce corresponding responses. A first request is duplicated to be redundantly processed independently and asynchronously by distinct shared agents to produce redundant counterpart responses including a first redundant response and a second redundant response. The first redundant response is compared against the second redundant response. In response to a match, the redundant responses are merged to produce a single final response to the first request to be read by the requestor node. In response to a non-match, an exception response is performed.

公开(公告)号：US20190163583A1

公开(公告)日：2019-05-30

申请号：US15823313

申请日：2017-11-27

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Swadesh Choudhary ,  Rahul Pal ,  Vedaraman Geetha

IPC: G06F11/16 ,  G06F11/14 ,  G06F11/18

Abstract: Operational faults, including transient faults, are detected within computing hardware for mission-critical applications. Operational requests received from a requestor node are to be processed by shared agents to produce corresponding responses. A first request is duplicated to be redundantly processed independently and asynchronously by distinct shared agents to produce redundant counterpart responses including a first redundant response and a second redundant response. The first redundant response is compared against the second redundant response. In response to a match, the redundant responses are merged to produce a single final response to the first request to be read by the requestor node. In response to a non-match, an exception response is performed.

公开(公告)号：US10248591B2

公开(公告)日：2019-04-02

申请号：US15393153

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert H. Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  H04L12/933 ,  G06F9/46 ,  G06F13/40 ,  G06F12/0813 ,  G06F12/0815 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808 ,  H04L12/741 ,  G06F8/73 ,  H04L12/46

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US10140213B2

公开(公告)日：2018-11-27

申请号：US15447767

申请日：2017-03-02

Applicant: Intel Corporation

Inventor： Robert G. Blankenship ,  Jeffrey D. Chamberlain ,  Yen-Cheng Liu ,  Vedaraman Geetha

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0893 ,  G06F12/126

Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

公开(公告)号：US20170109286A1

公开(公告)日：2017-04-20

申请号：US15393577

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Robert G. Blankenship ,  Bahaa Fahim ,  Robert H. Beers ,  Yen-Cheng Liu ,  Vedaraman Geetha ,  Herbert H. Hum ,  Jeff Willey

IPC: G06F12/0831 ,  G06F12/0808

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

Abstract: A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback.

公开(公告)号：US09606925B2

公开(公告)日：2017-03-28

申请号：US14669248

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Yen-Cheng Liu ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  Min Huang

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0855 ,  G06F12/0817 ,  G06F12/0831 ,  G06F2212/27 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, a processor includes a caching home agent (CHA) coupled to a core and a cache memory and includes a cache controller having a cache pipeline and a home agent having a home agent pipeline. The CHA may: receive, in the home agent pipeline, information from an external agent responsive to a miss for data in the cache memory; issue a global ordering signal from the home agent pipeline to a requester of the data to inform the requester of receipt of the data; and report issuance of the global ordering signal to the cache pipeline, to prevent the cache pipeline from issuance of a global ordering signal to the requester. Other embodiments are described and claimed.

公开(公告)号：US09436605B2

公开(公告)日：2016-09-06

申请号：US14136131

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Jeffrey D. Chamberlain ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Adrian C. Moga ,  Herbert H. Hum ,  Sailesh Kottapalli

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/0815

Abstract: An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.

Abstract translation: 一种用于减少或消除写回操作的设备和方法。 例如，方法的一个实施例包括：在第一请求者高速缓存处检测与高速缓存行相关联的第一操作; 检测到所述高速缓存行存在于修改（M）状态的第一高速缓存中; 将所述高速缓存行从所述第一高速缓存转发到所述第一请求者高速缓存，并且以第二修改（M'）状态将所述高速缓存行存储在所述第一请求程序高速缓存中; 在第二请求者处检测与所述高速缓存线相关联的第二操作; 响应地将所述高速缓存行从所述第一请求者缓存转发到所述第二请求器高速缓存，并且如果所述高速缓存行尚未在所述第一请求者高速缓存中被修改则将所述高速缓存行存储在所述第二请求程序高速缓存中; 以及将所述高速缓存行设置为所述第一请求者缓存中的共享（S）状态。

公开(公告)号：US09405687B2

公开(公告)日：2016-08-02

申请号：US14070864

申请日：2013-11-04

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Samuel D. Strom ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Krishnakumar Ganapathy ,  Cesar Maldonado

IPC: G06F12/08

CPC classification number: G06F12/0813 ,  G06F12/0831 ,  G06F12/0884 ,  G06F2212/2542 ,  Y02D10/13

Abstract: In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion includes a cache controller to receive a read request for data and, responsive to the data not being present in a cache memory associated with the cache controller, to issue a memory request to a memory controller to request the data in parallel with communication of the memory request to a home agent, where the home agent is to receive the memory request from the cache controller and to reserve an entry for the memory request. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括一个或多个核心和分布式缓存归属代理（包括与每个核心相关联的部分）。 每个部分包括高速缓存控制器，用于接收对数据的读取请求，并且响应于不存在于与高速缓存控制器相关联的高速缓冲存储器中的数据，向存储器控制器发出存储器请求以与 对归属代理的存储器请求，其中归属代理将从高速缓存控制器接收存储器请求并且为存储器请求保留条目。 描述和要求保护其他实施例。