公开(公告)号：US10892225B2

公开(公告)日：2021-01-12

申请号：US16336582

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522

Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.

公开(公告)号：US20200279793A1

公开(公告)日：2020-09-03

申请号：US16643816

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Jianyong XIE ,  Yidnekachew S. Mekonnen ,  Zhiguo Qian ,  Kemal Aygun

IPC: H01L23/48 ,  H01L25/18 ,  H01L23/538 ,  H01L23/522 ,  H01L23/528 ,  H01L23/66 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498

Abstract: An electronic device package is described. The electronic device package includes one or more dies. The electronic device package includes an interposer coupled to the one or more dies. The electronic device package also includes a package substrate coupled to the interposer. The electronic device package includes a plurality of through-silicon vias (TSVs) in at least one die of the one or more dies, or the interposer, or both. The electronic device package includes a passive equalizer structure communicatively coupled to a TSV pair in the plurality of TSVs. The passive equalizer structure is operable to minimize a level of insertion loss variation in the TSV pair.

公开(公告)号：US10746780B2

公开(公告)日：2020-08-18

申请号：US15776979

申请日：2015-11-18

Applicant: Intel Corporation

Inventor： Mayue Xie ,  Simranjit S. Khalsa ,  Hemachandar Tanukonda Devarajulu ,  Deepak Goyal ,  Zhiguo Qian

IPC: G01R31/11 ,  G01R31/28 ,  G01R31/311

Abstract: An apparatus comprises a signal generator circuit, a test probe, a signal sensor circuit, and a defect detection circuit. The signal generator circuit is configured to generate an impulse test signal having an impulse waveform and adjust a bandwidth of the impulse test signal. The test probe is electrically coupled to the signal generator circuit and configured to apply the impulse test signal to a device under test (DUT). The signal sensor circuit is configured to sense a conducted test signal produced by applying the impulse test signal to the DUT with the test probe. The defect detection circuit is configured to generate an indication of a defect in the DUT using the conducted test signal.

公开(公告)号：US20200243448A1

公开(公告)日：2020-07-30

申请号：US15774306

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： Zhiguo Qian ,  Jianyong Xie ,  Kemal Aygun

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.

公开(公告)号：US10607951B2

公开(公告)日：2020-03-31

申请号：US15774958

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos Zhang ,  Gabriel Regalado Silva ,  Zhiguo Qian ,  Kemal Aygun

IPC: H01L23/66 ,  H01L23/48 ,  H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01P3/06 ,  H01P11/00

Abstract: A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device.

公开(公告)号：US20200098621A1

公开(公告)日：2020-03-26

申请号：US16140398

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Kaladhar Radhakrishnan ,  Zhiguo Qian ,  Johanna M. Swan

IPC: H01L21/768

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a first surface and an opposing second surface, wherein the first die is in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor may include a first conductive pillar at least partially surrounded by a magnetic material, and a second conductive pillar coupled to the first conductive pillar; and a second die having a first surface and an opposing second surface, wherein the second die is in a second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic core inductor.

公开(公告)号：US20200091128A1

公开(公告)日：2020-03-19

申请号：US16161578

申请日：2018-10-16

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Shawna M. Liff ,  Zhiguo Qian ,  Johanna M. Swan

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/532 ,  H01L23/66 ,  H01L23/538

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar.

公开(公告)号：US20180240788A1

公开(公告)日：2018-08-23

申请号：US15755533

申请日：2015-08-31

Applicant: Intel Corporation

Inventor： Daniel Sobieski ,  Kristof Darmawikarta ,  Sri Ranga Sai Boyapati ,  Merve Celikkol ,  Kyu Oh Lee ,  Kemal Aygun ,  Zhiguo Qian

IPC: H01L25/18 ,  H01L23/14 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry.

公开(公告)号：US10056528B1

公开(公告)日：2018-08-21

申请号：US15475219

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun

IPC: H01L21/44 ,  H01L23/04 ,  H01L33/38 ,  H01L23/498 ,  H01L25/07 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L33/382 ,  H01L21/486 ,  H01L23/147 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/073

Abstract: An interposer structure includes a plurality of front side contact interface structures for connecting the interposer structure to at least one other structure. Additionally, the interposer structure includes a plurality of back side contact interface structures for connecting the interposer structure to at least one other structure. Further, the interposer structure includes a first through substrate via and an electrically conductive shielding structure. The electrically conductive shielding structure ends before reaching a back side of the interposer substrate die and the first through substrate via is connected to the electrically conductive shielding structure at a front side of the interposer substrate die.

公开(公告)号：US20150011050A1

公开(公告)日：2015-01-08

申请号：US14495396

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及可嵌入封装组件中的桥互连组件的技术和配置。 在一个实施例中，包装组件包括被配置为在第一管芯和第二管芯之间布置电信号的封装衬底和嵌入在封装衬底中并被配置为在第一管芯和第二管芯之间布置电信号的桥， 包括桥接基板，通过桥接基板形成的一个或多个通孔通孔（THV）和布置在桥接基板的表面上的一个或多个走线，以在第一管芯和第二管芯之间布置电信号。 包括迹线和桥互连组件的接地平面的布线特征可以由气隙分开。 可以描述和/或要求保护其他实施例。