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    Gate structure integration scheme for fin field effect transistors
    36.
    发明授权
    Gate structure integration scheme for fin field effect transistors 有权
    翅片场效应晶体管的栅极结构集成方案

    公开(公告)号：US09583585B2

    公开(公告)日：2017-02-28

    申请号：US14985711

    申请日：2015-12-31

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

    IPC: H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L21/033

    CPC classification number: H01L29/4966 ,  H01L21/0337 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

    Abstract: In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence.

    Abstract translation: 在一个实施例中，提供一种半导体器件，其包括存在于鳍结构的沟道部分上的栅极结构。 栅极结构包括与栅极电介质的侧壁和栅极导体接触的电介质间隔物。 外延源极和漏极区域存在于鳍状结构的相对的侧壁上，其中与翅片结构的侧壁接触的外延源区域和外延漏极区域的表面与电介质间隔物的外表面对齐。 在一些实施例中，使用单个光致抗蚀剂掩模替换栅极序列形成半导体器件的电介质间隔物，栅极电介质和栅极导体。

    Self-aligned contact process enabled by low temperature
    40.
    发明授权
    Self-aligned contact process enabled by low temperature 有权
    自对准接触过程由低温启用

    公开(公告)号：US09324830B2

    公开(公告)日：2016-04-26

    申请号：US14227345

    申请日：2014-03-27

    Applicant: International Business Machines Corporation

    Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/283 ,  H01L29/165

    CPC classification number: H01L23/535 ,  H01L21/283 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

    Abstract: Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity.

    Abstract translation: 通过在衬底的半导体层的一部分上形成金属栅极结构来制造半导体器件的自对准接触。 金属栅极结构接触栅极间隔物的内侧壁。 在第一牺牲外延层上形成第二牺牲外延层。 第一牺牲外延层与栅极间隔物相邻并形成在半导体层的源/漏区上。 第一和第二牺牲外延层是凹进的。 凹陷暴露出源极/漏极区域的至少一部分。 第一电介质层形成在源极/漏极区域的暴露部分上并且在栅极间隔物和金属栅极结构之上。 在源极/漏极区域的至少一个暴露部分之上形成第一介电层内的至少一个空腔。 在至少一个空腔内形成至少一个金属接触件。

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