公开(公告)号：US09099393B2

公开(公告)日：2015-08-04

申请号：US13959375

申请日：2013-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDARIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Wing L. Lai ,  Vijay Narayanan ,  Ravikumar Ramachandran

IPC: H01L21/28 ,  H01L27/092

CPC classification number: H01L21/28229 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.

Abstract translation: 一种用于半导体制造的方法包括在栅腔中的介电层上形成扩散阻挡层和含金属层中的至少一个。 执行第一退火以将元件从扩散阻挡层和含金属层中的至少一个扩散到电介质层中。 去除含金属层和扩散阻挡层。 执行第二次退火以调节介电层中的元件的扩散以提供栅极电介质区域。

公开(公告)号：US08999831B2

公开(公告)日：2015-04-07

申请号：US13680257

申请日：2012-11-19

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/3205 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; annealing the structure at a high temperature of not less than 800° C.; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. Optionally, a second annealing step can be performed after the first anneal. This second anneal is performed as a millisecond anneal using a flash lamp or a laser.

Abstract translation: 一种制造用于半导体器件的替代栅极堆叠的方法包括在去除伪栅极之后的以下步骤：在由虚拟栅极腾出的区域上生长高k电介质层; 在高k电介质层上沉积薄金属层; 在所述薄金属层上沉积牺牲层; 在不低于800℃的高温下退火该结构; 去除牺牲层; 以及沉积用于间隙填充的低电阻率金属的金属层。 任选地，可以在第一退火之后执行第二退火步骤。 使用闪光灯或激光器作为毫秒退火来执行该第二退火。

公开(公告)号：US11216595B2

公开(公告)日：2022-01-04

申请号：US16578319

申请日：2019-09-21

Applicant: International Business Machines Corporation

Inventor： Richard H. Boivie ,  Eduard A. Cartier ,  Daniel J. Friedman ,  Kohji Hosokawa ,  Charanjit Jutla ,  Wanki Kim ,  Chandrasekara Kothandaraman ,  Chung Lam ,  Frank R. Libsch ,  Seiji Munetoh ,  Ramachandran Muralidhar ,  Vijay Narayanan ,  Dirk Pfeiffer ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Robert L. Wisnieff

IPC: G06F21/72 ,  G06F21/75 ,  G11C16/00

Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

公开(公告)号：US11152214B2

公开(公告)日：2021-10-19

申请号：US15133656

申请日：2016-04-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  John Bruley ,  Eduard A. Cartier ,  Martin M. Frank ,  Vijay Narayanan ,  John Rozen

IPC: H01L21/28 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.

公开(公告)号：US20210234096A1

公开(公告)日：2021-07-29

申请号：US17226495

申请日：2021-04-09

Applicant: TOKYO ELECTRON LIMITED ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Steven Consiglio ,  Cory Wajda ,  Kandabara Tapily ,  Takaaki Tsunomura ,  Takashi Ando ,  Paul C. Jamison ,  Eduard A. Cartier ,  Vijay Narayanan ,  Marinus J.P. Hopstaken

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing H2 gas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.

公开(公告)号：US10997321B2

公开(公告)日：2021-05-04

申请号：US16578321

申请日：2019-09-21

Applicant: International Business Machines Corporation

Inventor： Richard H. Boivie ,  Eduard A. Cartier ,  Daniel J. Friedman ,  Kohji Hosokawa ,  Charanjit Jutla ,  Wanki Kim ,  Chandrasekara Kothandaraman ,  Chung Lam ,  Frank R. Libsch ,  Seiji Munetoh ,  Ramachandran Muralidhar ,  Vijay Narayanan ,  Dirk Pfeiffer ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Robert L. Wisnieff

IPC: G06F21/72 ,  G06F21/75 ,  G11C16/00

Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

公开(公告)号：US20200020762A1

公开(公告)日：2020-01-16

申请号：US16032632

申请日：2018-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Martin M. Frank ,  Kam-Leung Lee ,  Eduard A. Cartier ,  Vijay Narayanan ,  Jean Fompeyrine ,  Stefan Abel ,  Oleg Gluschenkov ,  Hemanth Jagannathan

IPC: H01L29/04 ,  H01L21/02 ,  H01L29/51 ,  H01L29/06

Abstract: A method for converting a dielectric material including a type IV transition metal into a crystalline material that includes forming a predominantly non-crystalline dielectric material including the type IV transition metal on a supporting substrate as a component of an electrical device having a scale of microscale or less; and converting the predominantly non-crystalline dielectric material including the type IV transition metal to a crystalline crystal structure by exposure to energy for durations of less than 100 milliseconds and, in some instances, less than 10 microseconds. The resultant material is fully or partially crystallized and contains a metastable ferroelectric phase such as the polar orthorhombic phase of space group Pca21 or Pmn21. During the conversion to the crystalline crystal structure, adjacently positioned components of the electrical devices are not damaged.

公开(公告)号：US20190393413A1

公开(公告)日：2019-12-26

申请号：US16018715

申请日：2018-06-26

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Adam M. Pyzyna ,  John Bruley

IPC: H01L45/00 ,  H01L27/24

Abstract: CMOS-compatible non-filamentary RRAM devices and techniques for formation thereof are provided. In one aspect, a method of forming a non-filamentary RRAM device includes: depositing a base oxide layer (e.g., hafnium oxide) on a bottom electrode; depositing a cap layer (e.g., amorphous silicon) on the base oxide layer; and depositing a top electrode on the cap layer, wherein the cap layer and the top electrode are deposited in-situ without any air exposure in between such that there is an absence of oxide at an interface between the cap layer and the top electrode. A low resistivity layer can optionally be deposited on the top electrode. An RRAM device and a computing device having a crossbar array of the present RRAM cells are also provided.

公开(公告)号：US10505112B1

公开(公告)日：2019-12-10

申请号：US16018715

申请日：2018-06-26

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Adam M. Pyzyna ,  John Bruley

IPC: H01L27/24 ,  H01L45/00

Abstract: CMOS-compatible non-filamentary RRAM devices and techniques for formation thereof are provided. In one aspect, a method of forming a non-filamentary RRAM device includes: depositing a base oxide layer (e.g., hafnium oxide) on a bottom electrode; depositing a cap layer (e.g., amorphous silicon) on the base oxide layer; and depositing a top electrode on the cap layer, wherein the cap layer and the top electrode are deposited in-situ without any air exposure in between such that there is an absence of oxide at an interface between the cap layer and the top electrode. A low resistivity layer can optionally be deposited on the top electrode. An RRAM device and a computing device having a crossbar array of the present RRAM cells are also provided.

公开(公告)号：US10290700B2

公开(公告)日：2019-05-14

申请号：US15706126

申请日：2017-09-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Hemanth Jagannathan ,  Paul C. Jamison

IPC: H01L21/768 ,  H01L49/02 ,  H01L21/02 ,  H01L21/3205

Abstract: A tri-layer dielectric stack is provided for a metal-insulator-metal capacitor (MIMCAP). Also, a metal-insulator-metal capacitor (MIMCAP) is provided having three or more electrodes. The tri-layer dielectric stack includes a first layer formed from a first metal oxide electrical insulator. The tri-layer dielectric stack further includes a second layer, disposed over the first layer, formed from ZrO2. The tri-layer dielectric stack also includes a third layer, disposed over the second layer, formed from a second metal oxide electrical insulator.