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    METHOD OF CHANGING REFLECTANCE OR RESISTANCE OF A REGION IN AN OPTOELECTRONIC MEMORY DEVICE
    31.
    发明申请
    METHOD OF CHANGING REFLECTANCE OR RESISTANCE OF A REGION IN AN OPTOELECTRONIC MEMORY DEVICE 有权
    在光电存储器件中改变一个区域的反射或电阻的方法

    公开(公告)号：US20130258765A1

    公开(公告)日：2013-10-03

    申请号：US13765772

    申请日：2013-02-13

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

    IPC: G11C13/00

    CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C13/047 ,  G11C2013/0054 ,  H01L45/1213 ,  H01L45/145

    Abstract: A method for changing reflectance or resistance of a region in an optoelectronic memory device. Changing the reflectance of the region includes sending an electric current through the region to cause a reflectance change in the region. Changing the resistance of the region includes: projecting a laser beam at a first beam intensity on the region, resulting in the region changing from a first to a second different resistance value; electrically reading the second resistance value during which an optical signal carried by the laser beam has a first digital value; after electrically reading the second resistance value, the laser beam is projected at a second beam intensity on the region resulting in the region changing from the second to the first resistance value; and electrically reading the first resistance value of the region while the laser beam is being projected on the region at the second beam intensity.

    Abstract translation: 一种用于改变光电存储器件中的区域的反射率或电阻的方法。 改变该区域的反射率包括发送电流通过该区域以引起该区域中的反射率变化。 改变该区域的电阻包括：在区域上以第一光束强度投射激光束，导致区域从第一个不同的电阻值改变到第二个不同的电阻值; 电读取激光束携带的光信号具有第一数字值的第二电阻值; 在电读取第二电阻值之后，激光束在该区域上以第二光束强度投影，导致区域从第二电阻值变化到第一电阻值; 并且在激光束以第二光束强度投影在该区域上时电读取该区域的第一电阻值。

    3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY
    32.
    发明申请
    3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY 失效
    具有改进可靠性的浮动导电板的3D VIA电容器

    公开(公告)号：US20130164905A1

    公开(公告)日：2013-06-27

    申请号：US13771435

    申请日：2013-02-20

    Applicant: International Business Machines Corporation

    Inventor： Chih-Chao Yang ,  Fen Chen ,  Baozhen Li

    IPC: H01L49/02

    CPC classification number: H01L23/5223 ,  H01L21/76805 ,  H01L25/0657 ,  H01L28/91 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.

    Abstract translation: 本发明提供一种3D通孔电容器及其形成方法。 电容器包括在基板上的绝缘层。 绝缘层具有通孔，其具有侧壁和底部。 第一电极覆盖通孔的侧壁和底部的至少一部分。 第一高k电介质材料层覆盖在第一电极上。 第一导电板在第一高k电介质材料层之上。 第二高k电介质材料层覆盖在第一导电板上并留下未填充的通孔的剩余部分。 在通孔的剩余部分中形成第二电极。 第一导电板基本上平行于第一电极并且不与第一和第二电极接触。 还提供了这种3D通孔电容器的阵列。

    NON-CONTIGUOUS DUMMY STRUCTURE SURROUNDING THROUGH-SUBSTRATE VIA NEAR INTEGRATED CIRCUIT WIRES
    38.
    发明申请
    NON-CONTIGUOUS DUMMY STRUCTURE SURROUNDING THROUGH-SUBSTRATE VIA NEAR INTEGRATED CIRCUIT WIRES 审中-公开
    通过靠近集成电路的通过基底的非连续的结构

    公开(公告)号：US20160148863A1

    公开(公告)日：2016-05-26

    申请号：US14549846

    申请日：2014-11-21

    Applicant: International Business Machines Corporation

    Inventor： Fen Chen ,  Mukta G. Farooq ,  John M. Safran

    IPC: H01L23/498 ,  H01L21/48

    CPC classification number: H01L21/4885 ,  H01L23/481 ,  H01L23/522 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A three-dimensional (3-D) integrated circuit wiring including a plurality of stacked dielectric levels formed on a substrate includes a plurality of non-contiguous dummy walls patterned in a corresponding dielectric level around a circuit wire keep out zone (KOZ). The non-contiguous dummy walls are formed in the circuit wire KOZ and have an outer side and an opposing inner side that extend along a first direction to define a length. A circuit wire segment is located at a first metal level and a second circuit wire segment is located at a second metal level different from the first metal level. The first and second metal levels are located adjacent the inner side of at least one non-contiguous dummy wall.

    Abstract translation: 包括形成在基板上的多个堆叠电介质层的三维（3-D）集成电路布线包括在电路线保持区（KOZ）周围的相应电介质层中图案化的多个不连续的虚设壁。 不连续的虚设壁形成在电路线KOZ中，具有沿着第一方向延伸以限定长度的外侧和相对的内侧。 电路线段位于第一金属水平处，并且第二电路线段位于不同于第一金属水平的第二金属水平处。 第一和第二金属水平位于邻近至少一个不连续的虚拟壁的内侧。

    ELECTROMIGRATION MONITOR
    40.
    发明申请
    ELECTROMIGRATION MONITOR 有权
    电气监控

    公开(公告)号：US20150380326A1

    公开(公告)日：2015-12-31

    申请号：US14320598

    申请日：2014-06-30

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Fen Chen ,  Mukta G. Farooq ,  John A. Griesemer ,  Chandrasekaran Kothandaraman ,  John M. Safran ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

    IPC: H01L21/66 ,  G01R31/08 ,  H01L23/48

    CPC classification number: G01R31/08 ,  G01R31/2856 ,  G01R31/2858 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

    Abstract translation: 诸如晶片，芯片，IC，设计结构等的结构包括硅通孔（TSV）和电迁移（EM）监视器。 TSV完全延伸穿过半导体芯片，并且EM监测器包括围绕TSV周边近似排列的多个EM电线。 EM测试方法包括强制电流通过紧邻TSV周界布置的EM监测器接线，测量EM监测器接线两端的电阻降，确定在EM监测器接线和TSV之间是否存在电短路 测量的电阻，和/或确定由于TSV引起的接近效应，EM监测布线内是否存在早期电开路或电阻增加。

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