公开(公告)号：US20150140698A1

公开(公告)日：2015-05-21

申请号：US14607161

申请日：2015-01-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

IPC: H01L21/66 ,  H01L21/8234

CPC classification number: H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

公开(公告)号：US20150140697A1

公开(公告)日：2015-05-21

申请号：US14607160

申请日：2015-01-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

IPC: H01L21/66 ,  H01L21/8234

CPC classification number: H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

Abstract translation: 提供了一种使用多重图案化光刻工艺（MPLP）形成具有测试宏的集成电路的方法。 该方法包括在MPLP的第一步骤期间形成具有第一和第二栅极区的测试宏的有源区，以及在MPLP的第二步骤期间在有源区中形成第一和第二源/漏区。 该方法还包括形成连接到第一栅极区域的第一触点，连接到第二栅极区域的第二触点，连接到第一源极/漏极区域的第三触点和连接到源极/漏极区域的第四触点和确定 如果通过测试第一接触，第二接触，第三接触或第四接触中的一个或多个之间的短路，在MPLP的步骤的第一步骤和第二步骤之间发生覆盖移位。

公开(公告)号：US11443982B2

公开(公告)日：2022-09-13

申请号：US16183785

申请日：2018-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andrew Greene ,  Ruilong Xie ,  Laertis Economikos ,  Veeraraghavan S. Basker ,  Chanro Park ,  Hui Zang

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: A semiconductor device includes one or more fins extending from a substrate, the one or more fins having source/drain epitaxial grown material (S/D epitaxy) thereon that merges one or more fins, a gate formed over the one or more fins, the gate including high k metal gate disposed between gate spacers and a metal liner over the S/D epitaxy and sides of the gate spacers. The gate includes a self-aligned contact cap over the HKMG and the metal liner.

公开(公告)号：US20200152509A1

公开(公告)日：2020-05-14

申请号：US16183785

申请日：2018-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andrew Greene ,  Ruilong Xie ,  Laertis Economikos ,  Veeraraghavan S. Basker ,  Chanro Park ,  Hui Zang

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234

Abstract: A semiconductor device includes one or more fins extending from a substrate, the one or more fins having source/drain epitaxial grown material (S/D epitaxy) thereon that merges one or more fins, a gate formed over the one or more fins, the gate including high k metal gate disposed between gate spacers and a metal liner over the S/D epitaxy and sides of the gate spacers. The gate includes a self-aligned contact cap over the HKMG and the metal liner.

公开(公告)号：US10388769B2

公开(公告)日：2019-08-20

申请号：US15815626

申请日：2017-11-16

Applicant: International Business Machines Corporation

Inventor： Miaomiao Wang ,  Tenko Yamashita ,  Chun-chen Yeh ,  Hui Zang

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234

Abstract: In a fin-Field Effect Transistor (finFET), a recess is created at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into a substrate interfacing with the gate. The recess is filled at least partially with a first conductive material. The first conductive material is insulated from the gate. The fin is replaced with a replacement structure. The replacement structure is electrically connected to the first conductive material using a second conductive material. The second conductive material is insulated from a first surface of the finFET. A first electrical contact structure is fabricated on the first surface. A second electrical contact structure is fabricated on a second surface of the finFET, the second surface being on a different spatial plane than the first surface.

公开(公告)号：US09564440B2

公开(公告)日：2017-02-07

申请号：US15232246

申请日：2016-08-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

Abstract translation: 一种形成用于半导体器件的栅极结构的方法，包括在存在于鳍状结构上的置换栅极结构的侧壁上形成第一间隔物，其中第一间隔物的上表面偏离替换栅极结构的上表面 并且在所述第一间隔物和所述替换栅极结构的所述暴露表面上形成至少第二间隔物。 该方法还可以包括用相邻的第一间隔件之间的第一空间中具有第一宽度部分的功能栅极结构代替替换栅极结构，以及在相邻的第二间隔物之间​​的第二空间中具有第二宽度的第二宽度部分，其中第二 宽度大于第一宽度。

公开(公告)号：US20170025285A1

公开(公告)日：2017-01-26

申请号：US14805527

申请日：2015-07-22

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Jin Cho ,  MiaoMiao Wang ,  Hui Zang

IPC: H01L21/321 ,  H01L21/28 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/513 ,  H01L21/28026 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation.

公开(公告)号：US20170005014A1

公开(公告)日：2017-01-05

申请号：US14789476

申请日：2015-07-01

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

IPC: H01L21/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L22/32 ,  H01L21/76895 ,  H01L21/823431 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7851

Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

Abstract translation: 实施例涉及一种方法。实施例涉及鳍式场效应晶体管（FinFET）的测试结构。 测试结构包括电耦合到FinFET的伪栅极的第一导电层和电耦合到FinFET的衬底的第二导电层。 测试结构还包括电耦合到FinFET的伪栅极的第三导电层，以及至少部分地由第一导电层和第二导电层限制的FinFET的第一区域。 所述测试结构还包括至少部分地由所述第二导电层和所述第三导电层限制的所述FinFET的第二区域，其中所述第一区域包括具有第一尺寸的第一电介质，并且其中所述第二区域包括具有 第二维度大于第一维度。

公开(公告)号：US09443944B2

公开(公告)日：2016-09-13

申请号：US14541754

申请日：2014-11-14

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hui Zang ,  Balasubramanian Pranatharthiharan

IPC: H01L29/417 ,  H01L29/40 ,  H01L21/28

CPC classification number: H01L29/41783 ,  H01L21/28008 ,  H01L21/76801 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/401 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with middle of line capacitance reduction in self-aligned contact process flow and fabrication are provided. One method includes, for instance: obtaining a wafer with at least one source, drain, and gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; and forming at least one first and second small contact over the first and second contact regions. One intermediate semiconductor device includes, for instance: a wafer with a gate, source region, and drain region; at least one first contact region positioned over a portion of the source; at least one second contact region positioned over a portion of the drain; at least one first small contact positioned above the first contact region; and at least one second small contact positioned above the second contact region.

Abstract translation: 提供了用于形成具有自对准接触工艺流程和制造中线路电容减小的半导体器件的器件和方法。 一种方法包括例如：获得具有至少一个源极，漏极和栅极的晶片; 在所述至少一个源极上形成第一接触区域，以及在所述至少一个漏极上形成第二接触区域; 以及在所述第一和第二接触区域上形成至少一个第一和第二小接触。 一个中间半导体器件包括例如：具有栅极，源极区和漏极区的晶片; 位于所述源的一部分上方的至少一个第一接触区域; 至少一个第二接触区域位于所述排水管的一部分上方; 位于所述第一接触区域上方的至少一个第一小接触件; 以及位于第二接触区域上方的至少一个第二小接触件。

公开(公告)号：US10396183B2

公开(公告)日：2019-08-27

申请号：US15815605

申请日：2017-11-16

Applicant: International Business Machines Corporation

Inventor： Miaomiao Wang ,  Tenko Yamashita ,  Chun-chen Yeh ,  Hui Zang

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234

Abstract: In a fin-Field Effect Transistor (finFET), a recess is created at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into a substrate interfacing with the gate. The recess is filled at least partially with a first conductive material. The first conductive material is insulated from the gate. The fin is replaced with a replacement structure. The replacement structure is electrically connected to the first conductive material using a second conductive material. the second conductive material is insulated from a first surface of the finFET. A first electrical contact structure is fabricated on the first surface. A second electrical contact structure is fabricated on a second surface of the finFET, the second surface being on a different spatial plane than the first surface.