公开(公告)号：US20190355668A1

公开(公告)日：2019-11-21

申请号：US15983689

申请日：2018-05-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Rizzolo ,  Chih-Chao Yang ,  Lawrence A. Clevenger ,  Benjamin D. Briggs

IPC: H01L23/544 ,  H01L27/22

Abstract: A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

公开(公告)号：US20190318960A1

公开(公告)日：2019-10-17

申请号：US16451269

申请日：2019-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Terry A. Spooner ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311 ,  H01L21/3105

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

公开(公告)号：US20190313533A1

公开(公告)日：2019-10-10

申请号：US15949741

申请日：2018-04-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Spyridon Skordas ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Benjamin D. Briggs ,  Michael Rizzolo ,  Maryam Ashoori ,  Arvind Kumar

IPC: H05K3/28 ,  H01L25/00 ,  H01L33/52 ,  H01L25/16 ,  H01L21/56 ,  H05K3/30

Abstract: Methods for orientation and placement of computing devices are presented. Aspects include applying, using a viscous material application device, a layer of a viscous material to a surface of an object, the layer of the viscous material having a plurality of computing devices disposed therein. The layer of the viscous material is allowed to dry during a drying period, wherein each of the plurality of computing devices comprises a first material applied to a first side of each of the plurality of computing devices, the first material having a first characteristic. And each of the plurality of computing devices comprises a second material applied to a second side of each of the plurality of computing devices, the second material having a second characteristic. And each of the plurality of computing devices is configured to perform, during the drying period, a self-orientation operation.

公开(公告)号：US20190304733A1

公开(公告)日：2019-10-03

申请号：US16427918

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo

IPC: H01J21/10 ,  G06F17/50 ,  H01J19/24 ,  H01J9/02

Abstract: A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned.

公开(公告)号：US10388525B2

公开(公告)日：2019-08-20

申请号：US15810454

申请日：2017-11-13

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Sean D. Burns ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3115

Abstract: Multi-angled deposition and masking techniques are provided to enable custom trimming and selective removal of spacers that are used for patterning features at sub-lithographic dimensions. For example, a method includes forming a sacrificial mandrel on a substrate, and forming first and second spacers on opposing sidewalls of the sacrificial mandrel. The first and second spacers are formed with an initial thickness Ts. A first angle deposition process is performed to deposit a material (e.g., insulating material or metallic material) at a first deposition angle A1 to form a first trim mask layer on an upper portion of the first spacer and the sacrificial mandrel while preventing the material from being deposited on the second spacer. A spacer etch process is performed to trim the first spacer to a first thickness T1, which is less than Ts, using the first trim mask layer as an etch mask.

公开(公告)号：US10347825B2

公开(公告)日：2019-07-09

申请号：US15436001

申请日：2017-02-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Joe Lee ,  Christopher J. Penny ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L43/06 ,  H01L43/12 ,  H01L43/08

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, and etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches. The method further includes selectively depositing an electrode over the top surface of the exposed metal and nitridizing the electrode to form a diffusion barrier between chip components and the metal.

公开(公告)号：US20190181091A1

公开(公告)日：2019-06-13

申请号：US15839505

申请日：2017-12-12

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L23/525 ,  H01L23/532

Abstract: Techniques facilitating back end of line electrical fuse structure and method of fabrication are provided. A device can comprise a first metal interconnect formed in a dielectric layer of a semiconductor chip. The device can also comprise a second metal interconnect formed in the dielectric layer and adjacent to the first metal interconnect. Further, the device can comprise a vertical electrical fuse element comprising a first portion of a conductive material deposited on a first surface of the first metal interconnect and a second portion of the conductive material deposited on a second surface of the second metal interconnect. The vertical electrical fuse element can comprise a first region comprising a first thickness and a second region comprising a second thickness different than the first thickness.

公开(公告)号：US10243020B1

公开(公告)日：2019-03-26

申请号：US15799502

申请日：2017-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Nicholas A. Lanzillo ,  Michael Rizzolo ,  Theodorus E. Standaert

IPC: H01L29/82 ,  H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02

Abstract: A magnetic random access memory (MRAM) device includes a conductor disposed in an insulating material of a lower wiring layer, a magnetic tunnel junction (MTJ) structure formed in an upper wiring layer, and a landing pad formed in an intermediary wiring layer between the lower and upper wiring layers, the landing pad extending from a top surface of the conductor to a height above the intermediary wiring layer, wherein the landing pad connects the MJT structure to the conductor.

公开(公告)号：US10134674B2

公开(公告)日：2018-11-20

申请号：US15676263

申请日：2017-08-14

Applicant: International Business Machines Corporation

Inventor： Benjamin David Briggs ,  James J. Kelly ,  Koichi Motoyama ,  Roger Allan Quon ,  Michael Rizzolo ,  Theodorus Eduardus Standaert

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/288

Abstract: A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.

公开(公告)号：US10083905B2

公开(公告)日：2018-09-25

申请号：US15426679

申请日：2017-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Bartlet H. DeProspo ,  Huai Huang ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53238

Abstract: A method of forming a skip-via, including, forming a first dielectric layer on a first metallization layer, forming a second metallization layer on the first dielectric layer and a second dielectric layer on the second metallization layer, removing a section of the second dielectric layer to form a via to the second metallization layer, removing a portion of the second metallization layer to form an aperture, and removing an additional portion of the second metallization layer to form an exclusion zone.