公开(公告)号：US10204999B2

公开(公告)日：2019-02-12

申请号：US15743847

申请日：2015-07-17

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Joodong Park ,  En-Shao Liu ,  Everett S. Cassidy-Comfort ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L21/764 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

公开(公告)号：US10192969B2

公开(公告)日：2019-01-29

申请号：US15327641

申请日：2014-08-19

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid Hafez ,  Hsu-Yu Chang ,  Roman Olac-Vaw ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3213 ,  H01L23/535 ,  H01L23/66 ,  H01L21/3115

Abstract: Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

公开(公告)号：US09947585B2

公开(公告)日：2018-04-17

申请号：US15127839

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Chia-Hong Jan ,  Roman W. Olac-Vaw ,  Hsu-Yu Chang ,  Neville L. Dias ,  Walid M. Hafez ,  Rahul Ramaswamy

IPC: H01L29/78 ,  H01L29/76 ,  H01L27/088 ,  H01L21/283 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L21/823412 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42368 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, a drain region having a drain width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the apparatus includes at least one of (a) the channel region width being wider than the source region width, and (b) the gate dielectric including a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location, the first and second locations located at an equivalent height on the sidewall and the first and second gate dielectrics thicknesses being unequal to one another. Other embodiments are described herein.

公开(公告)号：US09865695B2

公开(公告)日：2018-01-09

申请号：US14673163

申请日：2015-03-30

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Chia-Hong Jan ,  Anisur Rahman

IPC: H01L29/45 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49

CPC classification number: H01L29/45 ,  H01L21/823418 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

Abstract: An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.

公开(公告)号：US09842944B2

公开(公告)日：2017-12-12

申请号：US15121879

申请日：2014-07-14

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/80 ,  H01L29/8605 ,  H01L29/40 ,  H01L29/66 ,  H01L29/808 ,  H01L29/06

CPC classification number: H01L29/0649 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/404 ,  H01L29/66166 ,  H01L29/66803 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8605

Abstract: A solid source-diffused junction is described for fin-based electronics. In one example, a fin is formed on a substrate. A glass of a first dopant type is deposited over the substrate and over a lower portion of the fin. A glass of a second dopant type is deposited over the substrate and the fin. The glass is annealed to drive the dopants into the fin and the substrate. The glass is removed and a first and a second contact are formed over the fin without contacting the lower portion of the fin.

公开(公告)号：US09780217B2

公开(公告)日：2017-10-03

申请号：US14780218

申请日：2013-06-26

Applicant: Intel Corporation

Inventor： Jeng-Ya D. Yeh ,  Chia-Hong Jan ,  Walid M. Hafez ,  Joodong Park

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L29/42368 ,  H01L29/66795 ,  H01L29/785

Abstract: Non-planar semiconductor devices having self-aligned fins with top blocking layers and methods of fabricating non-planar semiconductor devices having self-aligned fins with top blocking layers are described. For example, a semiconductor structure includes a semiconductor fin disposed above a semiconductor substrate and having a top surface. An isolation layer is disposed on either side of the semiconductor fin, and recessed below the top surface of the semiconductor fin to provide a protruding portion of the semiconductor fin. The protruding portion has sidewalls and the top surface. A gate blocking layer has a first portion disposed on at least a portion of the top surface of the semiconductor fin, and has a second portion disposed on at least a portion of the sidewalls of the semiconductor fin. The first portion of the gate blocking layer is continuous with, but thicker than, the second portion of the gate blocking layer. A gate stack is disposed on the first and second portions of the gate blocking layer.

公开(公告)号：US09741721B2

公开(公告)日：2017-08-22

申请号：US14912890

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Joodong Park ,  Gopinath Bhimarasetti ,  Rahul Ramaswamy ,  Chia-Hong Jan ,  Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/10826 ,  H01L27/10808 ,  H01L27/10879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854

Abstract: Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.

公开(公告)号：US20170125419A1

公开(公告)日：2017-05-04

申请号：US15409435

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L. Dias ,  Chanaka D. Munasinghe

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L21/225 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/2256 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/66803 ,  H01L29/7851

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.

公开(公告)号：US20170069758A1

公开(公告)日：2017-03-09

申请号：US15353631

申请日：2016-11-16

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Curtis Tsai ,  Jeng-Ya D. Yeh ,  Joodong Park

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L27/12 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.

Abstract translation: 描述了用于片上系统（SoC）应用的垂直非平面半导体器件和制造垂直非平面半导体器件的方法。 例如，半导体器件包括设置在衬底上方的半导体鳍片，半导体鳍片具有凹部和最上部。 源极区域设置在半导体鳍片的凹部中。 漏极区域设置在半导体鳍片的最上部。 栅电极设置在半导体鳍片的最上部分之间，在源区和漏区之间。

公开(公告)号：US20170025533A1

公开(公告)日：2017-01-26

申请号：US15301282

申请日：2014-06-20

Applicant: Kinyip PHOA ,  Nidhi NIDHI ,  Chia-Hong JAN ,  Ting CHANG ,  INTEL CORPORATION

Inventor： Kinyip Phoa ,  Nidhi Nidhi ,  Chia-Hong Jan ,  Ting Chang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7834 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/66621 ,  H01L29/7835

Abstract: High voltage transistors spanning multiple non-planar semiconductor bodies, such as fins or nanowires, are monolithically integrated with non-planar transistors utilizing an individual non-planar semiconductor body. The non-planar FETs may be utilized for low voltage CMOS logic circuitry within an IC, while high voltage transistors may be utilized for high voltage circuitry within the IC. A gate stack may be disposed over a high voltage channel region separating a pair of fins with each of the fins serving as part of a source/drain for the high voltage device. The high voltage channel region may be a planar length of substrate recessed relative to the fins. A high voltage gate stack may use an isolation dielectric that surrounds the fins as a thick gate dielectric. A high voltage transistor may include a pair of doped wells formed into the substrate that are separated by the high voltage gate stack with one or more fin encompassed within each well.

Abstract translation: 跨越多个非平面半导体器件（例如鳍片或纳米线）的高压晶体管与利用单个非平面半导体器件的非平面晶体管单片集成。 非平面FET可用于IC内的低电压CMOS逻辑电路，而高电压晶体管可用于IC内的高电压电路。 栅极堆叠可以设置在高压通道区域上，该高压通道区域分离一对翅片，其中每个翅片用作高压设备的源极/漏极的一部分。 高压通道区域可以是相对于翅片凹进的基板的平面长度。 高压栅极堆叠可以使用围绕散热片的隔离电介质作为厚栅极电介质。 高压晶体管可以包括形成在衬底中的一对掺杂阱，其被高压栅极堆叠分隔开，其中一个或多个鳍包围在每个阱内。