公开(公告)号：US10056182B2

公开(公告)日：2018-08-21

申请号：US14616508

申请日：2015-02-06

Applicant: Intel Corporation

Inventor： Gregorio R. Murtagian ,  Robert L. Sankman ,  Brent S. Stone ,  Kaladhar Radhakrishnan ,  Joshua D. Heppner

IPC: H01F27/29 ,  H01F5/00 ,  H01F27/02 ,  H01L27/08 ,  H05K7/00 ,  H01F27/28 ,  H01F17/04 ,  H01F27/06

CPC classification number: H01F27/2852 ,  H01F17/045 ,  H01F27/02 ,  H01F27/027 ,  H01F27/06 ,  H01F27/2847 ,  H01F27/292 ,  H01F2027/065 ,  H01F2027/297 ,  H01L2224/16225 ,  H01L2924/181 ,  Y10T29/4902 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed.

公开(公告)号：US20180197845A1

公开(公告)日：2018-07-12

申请号：US15911958

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Yongki Min ,  Reynaldo A. Olmedo ,  William J. Lambert ,  Kaladhar Radhakrishnan ,  Leigh E. Wojewoda ,  Venkat Anil K. Magadala ,  Clive R. Hendricks

IPC: H01L25/18 ,  H01L25/065 ,  H01F17/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01F17/00 ,  H01F17/0006 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/06 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/16265 ,  H01L2924/1427 ,  H01L2924/143 ,  H01L2924/19011 ,  H01L2924/19042

Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.

公开(公告)号：US09911723B2

公开(公告)日：2018-03-06

申请号：US14974978

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Yongki Min ,  Reynaldo A. Olmedo ,  William J. Lambert ,  Kaladhar Radhakrishnan ,  Leigh E. Wojewoda ,  Venkat Anil K. Magadala ,  Clive R. Hendricks

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065 ,  H01L25/16 ,  H01F17/00

CPC classification number: H01L25/18 ,  H01F17/00 ,  H01F17/0006 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5227 ,  H01L24/06 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/16265 ,  H01L2924/1427 ,  H01L2924/143 ,  H01L2924/19011 ,  H01L2924/19042

Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.

公开(公告)号：US20170060205A1

公开(公告)日：2017-03-02

申请号：US14836780

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Srikrishnan Venkataraman ,  William J. Lambert ,  Michael J. Hill ,  Alexander Slepoy ,  Dong Zhong ,  Kaladhar Radhakrishnan ,  Hector A. Aguirre Diaz ,  Jonathan P. Douglas

IPC: G06F1/26 ,  H02J1/00 ,  G06F1/32 ,  H02M3/158

CPC classification number: G06F1/26 ,  G06F1/3203 ,  H01L23/645 ,  H02J1/00 ,  H02M3/158 ,  H02M3/1584 ,  H02M2001/008 ,  H02M2003/1586

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract translation: 描述了一种装置，其包括：耦合到第一一个或多个电感器的第一电压调节器（VR），第一VR为第一功率域提供电力; 以及耦合到第二一个或多个电感器的第二VR，其中至少一个电感器感应耦合到所述第一个或多个电感器中的至少一个，所述第二VR为与所述第一电源域分离的第二电力域提供电力， 其中在第一VR相对于第二VR的开关晶体管之间存在非零相位角偏移。

公开(公告)号：US20250103074A1

公开(公告)日：2025-03-27

申请号：US18474147

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Harish K. Krishnamurthy ,  Nicolas Butzen ,  Khondker Ahmed ,  Nachiket Desai ,  Su Hwan Kim ,  Krishnan Ravichandran ,  Kaladhar Radhakrishnan ,  Jonathan Douglas

IPC: G05F1/56

Abstract: Embodiments herein relate to a voltage regular (VR) formed from dies stacked on a package base layer. The VR can include a first part on a first die and a second part on a second die, where the different parts are selected based on characteristics of the respective die such as their voltage domains or technologies. In a capacitor-based VR, an input capacitor and switches subject to a relatively high input voltage can be provided in the first die, while a flying capacitor, output capacitor and switches subject to a relatively low output voltage can be provided in the second die. In an inductor-based VR, an inductor and one or more switches subject to a relatively high input voltage can be provided in the first die, while an output capacitor subject to a relatively low output voltage can be provided in the second die.

公开(公告)号：US12068684B2

公开(公告)日：2024-08-20

申请号：US17030132

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Christopher Schaef ,  William J. Lambert ,  Kaladhar Radhakrishnan

IPC: H02M3/04 ,  H01F27/24 ,  H01L49/02 ,  H03K19/21

CPC classification number: H02M3/04 ,  H01F27/24 ,  H01L28/10 ,  H03K19/21

Abstract: Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.

公开(公告)号：US11710720B2

公开(公告)日：2023-07-25

申请号：US16022515

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  Siddharth Kulasekaran ,  Kaladhar Radhakrishnan

IPC: H01L25/065 ,  H01L25/18 ,  H02M1/08 ,  H02M3/158 ,  H02M1/00

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L25/18 ,  H02M1/08 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H02M1/0009 ,  H02M3/158

Abstract: A semiconductor package is provided, which includes a first die and a second die. The first die includes a first section of a power converter, and the second die includes a second section of the power converter. The power converter may include a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches. The PM circuitry may include a first part and a second part. The first section of the power converter in the first die may include the first part of the PM circuitry, and the second section of the power converter in the second die may include the second part of the PM circuitry.

公开(公告)号：US11676950B2

公开(公告)日：2023-06-13

申请号：US16635147

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Krishna Bharath ,  Sriram Srinivasan ,  Amruthavalli Alur ,  Kaladhar Radhakrishnan ,  Huong Do ,  William Lambert

IPC: H01L23/498 ,  H01L23/64 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L25/16 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/642 ,  H01L23/645

Abstract: An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

公开(公告)号：US20230060727A1

公开(公告)日：2023-03-02

申请号：US17412810

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Kaladhar Radhakrishnan ,  Krishna Bharath ,  William J. Lambert ,  Adel A. Elsherbini ,  Sriram Srinivasan ,  Christopher Schaef

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.

公开(公告)号：US20220406701A1

公开(公告)日：2022-12-22

申请号：US17822200

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  G05F1/46 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.