公开(公告)号：US11024601B2

公开(公告)日：2021-06-01

申请号：US16348448

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20200025801A1

公开(公告)日：2020-01-23

申请号：US16586763

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Mark Bohr ,  Joe Walczyk

IPC: G01R1/073 ,  H01L23/14 ,  G01R31/28 ,  H01L21/027 ,  H01L21/48 ,  H01L23/32 ,  H01L23/48

Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

公开(公告)号：US20240332100A1

公开(公告)日：2024-10-03

申请号：US18193172

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Pratyush Mishra ,  Marcel Wall ,  Sashi Kandanur ,  Pooya Tadayon ,  Srinivas Pietambaram ,  Benjamin Duong ,  Suddhasattwa Nad

IPC: H01L23/15 ,  H01F27/24 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L23/15 ,  H01F27/24 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5226

Abstract: Glass-integrated inductors in integrated circuit (IC) packages are disclosed. A disclosed IC package includes a glass layer having an aperture extending therethrough, and an inductor in the aperture, the inductor including a metal core extending through the aperture, the metal core electrically coupled to interconnects on opposite sides of the glass layer, and at least one of a ferrite or a magnetic alloy in the aperture and laterally surrounding the metal core.

公开(公告)号：US20240063134A1

公开(公告)日：2024-02-22

申请号：US18260805

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Xiaoning Ye ,  Pooya Tadayon ,  Wenzhi Wang ,  Srinivasa R. Aravamudhan ,  Nathan Somnang Tan ,  Brett Daniel Grossman

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L23/5383 ,  H01L23/49894 ,  H01L23/49877 ,  H01L2224/16225 ,  H01L24/16

Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and an individual conductive segment may have a conductivity that is close to or less than a conductivity of a conductive line of an individual microstrip.

公开(公告)号：US20240027706A1

公开(公告)日：2024-01-25

申请号：US17871473

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Eric J. M. Moret ,  Tarek A. Ibrahim ,  David Shia ,  Nicholas D. Psaila ,  Russell Childs

IPC: G02B6/42 ,  G02B6/43

CPC classification number: G02B6/4249 ,  G02B6/43 ,  G02B6/4214 ,  G02B6/4292

Abstract: In one embodiment, an integrated circuit device includes a substrate, an electronic integrated circuit (EIC), a photonics integrated circuit (PIC) electrically coupled to the EIC, and a glass block at least partially in a cavity defined by the substrate and at an end of the substrate. The glass block defines an optical path with one or more optical elements to direct light between the PIC and a fiber array unit (FAU) when attached to the glass block.

公开(公告)号：US11824041B2

公开(公告)日：2023-11-21

申请号：US17226967

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US11822249B2

公开(公告)日：2023-11-21

申请号：US17541162

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Pooya Tadayon

IPC: G03F7/20 ,  H01L27/00 ,  G03F7/30 ,  B05C3/04

CPC classification number: G03F7/2041 ,  B05C3/04 ,  G03F7/30 ,  G03F7/3021 ,  H01L27/00

Abstract: Disclosed is a method to develop lithographically defined high aspect ratio interconnects. Also disclosed is an apparatus comprising at least one vessel having a bottom and at least one sidewall extending from the bottom, wherein the at least one sidewall encloses an interior of the at least one vessel, a shaft having a proximal end and a distal end, wherein the distal end of the shaft extends into the interior of the at least one vessel, wherein the proximal end of the shaft is coupled to a motor, at least one support structure which extends laterally from the shaft, and a substrate attachment fixture on a distal end of the at least one support structure, wherein the at least one support structure and the substrate attachment fixture are within the interior of the at least one vessel.

公开(公告)号：US11774489B2

公开(公告)日：2023-10-03

申请号：US17343648

申请日：2021-06-09

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Justin Huttula

IPC: G01R31/28 ,  G01R3/00 ,  G01R1/067

CPC classification number: G01R31/2853 ,  G01R1/06738 ,  G01R3/00 ,  G01R31/2889

Abstract: A testing arrangement for testing Integrated Circuit (IC) interconnects is provided. In an example, the testing arrangement includes a substrate, and a first interconnect structure. The first interconnect structure may include a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end. In some examples, the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test.

公开(公告)号：US20230204879A1

公开(公告)日：2023-06-29

申请号：US17561818

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Dowon Kim ,  Suohai Mei ,  Pooya Tadayon ,  Jason Michael Gamba ,  Sanka Ganesan

IPC: G02B6/42

CPC classification number: G02B6/4214 ,  G02B6/4255 ,  G02B6/4245

Abstract: In one embodiment, an optical module includes an electronic integrated circuit, a photonic integrated circuit, and a pluggable optical coupling connector. The photonic integrated circuit sends or receives optical signals. The pluggable optical coupling connector is adjacent to the photonic integrated circuit and includes a pluggable interface to optically couple a fiber array to the photonic integrated circuit. Further, the electronic integrated circuit, the photonic integrated circuit, and the pluggable optical coupling connector are all embedded in a mold.

公开(公告)号：US20230204877A1

公开(公告)日：2023-06-29

申请号：US17561694

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： John M. Heck ,  Haisheng Rong ,  Harel Frish ,  Ankur Agrawal ,  Boping Xie ,  Randal S. Appleton ,  Hari Mahalingam ,  Alexander Krichevsky ,  Pooya Tadayon ,  Ling Liao ,  Eric J. M. Moret

IPC: G02B6/42

CPC classification number: G02B6/4207 ,  G02B6/4214 ,  G02B6/428

Abstract: Technologies for beam expansion and collimation for photonic integrated circuits (PICs) are disclosed. In one embodiment, an ancillary die is bonded to a PIC die. Vertical couplers in the PIC die direct light from waveguides to flat mirrors on a top side of the ancillary die. The flat mirrors reflect the light towards curved mirrors defined in the bottom surface of the ancillary die. The curved mirrors collimate the light from the waveguides. In another embodiment, a cavity is formed in a PIC die, and curved mirrors are formed in the cavity. Light beams from waveguides in the PIC die are directed to the curved mirrors, which collimate the light beams.