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    TRANSISTOR GATE STACKS WITH THICK HYSTERETIC ELEMENTS
    33.
    发明公开
    TRANSISTOR GATE STACKS WITH THICK HYSTERETIC ELEMENTS 审中-公开

    公开(公告)号：US20230307541A1

    公开(公告)日：2023-09-28

    申请号：US17702593

    申请日：2022-03-23

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand S. Murthy ,  Pushkar Sharad Ranade ,  Sagar Suthram

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

    CPC classification number: H01L29/78391 ,  H01L29/42364 ,  H01L29/516 ,  H01L29/6684

    Abstract: Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include thick hysteretic elements (i.e., hysteretic elements having a thickness of at least 10-15 nanometers, e.g., between 55 and 100 nanometers), and related methods and devices. Transistor gate stacks disclosed herein include a multilayer gate insulator having a thick hysteretic element and an interface layer, where the thick hysteretic element is between the interface layer and a gate electrode material, and the interface layer is between the thick hysteretic element and a channel material of a transistor. The interface layer may be a dielectric material with an effective dielectric constant of at least 20 and/or be a dielectric material that is thinner than about 3 nanometers. Such an interface layer may help improve gate control and allow use of thick hysteretic elements while maintaining transistor performance in terms of, e.g., gate leakage, carrier mobility, and subthreshold swing.

    INTEGRATED CIRCUIT DEVICES WITH ANGLED TRANSISTORS FORMED BASED ON ANGLED WAFERS
    34.
    发明公开
    INTEGRATED CIRCUIT DEVICES WITH ANGLED TRANSISTORS FORMED BASED ON ANGLED WAFERS 审中-公开

    公开(公告)号：US20230268382A1

    公开(公告)日：2023-08-24

    申请号：US17677239

    申请日：2022-02-22

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Wilfred Gomes ,  Sagar Suthram

    IPC: H01L29/04 ,  H01L29/06 ,  H01L29/66

    CPC classification number: H01L29/045 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/42392

    Abstract: IC devices including angled transistors formed based on angled wafers are disclosed. An example IC device includes a substrate and a semiconductor structure. A crystal direction of a crystal structure in the semiconductor structure is not aligned with a corresponding crystal direction (e.g., having same Miller indices) of a crystal structure in the substrate. An angle between the two crystal directions may be 4-60 degrees. The semiconductor structure is formed based on another substrate (e.g., a wafer) that has a different orientation from the substrate, e.g., flats or notches of the two substrates are not aligned. The crystal direction of the semiconductor structure may be determined based on a crystal direction in the another substrate. The semiconductor structure may be a portion of a transistor, e.g., the channel region and S/D regions of the transistor. The semiconductor structure may be angled with respect to an edge of the substrate.

    INTEGRATED CIRCUIT DEVICES WITH CONDUCTIVE LINES EXTENDING OVER SCRIBE LINES
    35.
    发明申请
    INTEGRATED CIRCUIT DEVICES WITH CONDUCTIVE LINES EXTENDING OVER SCRIBE LINES 有权

    公开(公告)号：US20240429162A1

    公开(公告)日：2024-12-26

    申请号：US18340072

    申请日：2023-06-23

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Sagar Suthram ,  Anand S. Murthy ,  Wilfred Gomes

    IPC: H01L23/528

    Abstract: An example IC device includes a substrate comprising a plurality of areas and one or more scribe lines defining boundaries of individual areas of the plurality of areas. The plurality of areas includes a first area and a second area. The IC device further includes a scribe line between the first area and the second area, a first device layer over the first area of the substrate and a first metallization stack over the first device layer, a second device layer over the second area of the substrate and a second metallization stack over the second device layer, and a conductive line extending (e.g., being materially and electrically continuous) between the first metallization stack and the second metallization stack, where a projection of the conductive line onto a plane parallel to the substrate and containing the scribe line intersects the scribe line.

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