中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

583 records (took 0.023 seconds)

    TRANSISTOR GATE STACKS WITH THICK HYSTERETIC ELEMENTS
    31.
    发明公开
    TRANSISTOR GATE STACKS WITH THICK HYSTERETIC ELEMENTS 审中-公开

    公开(公告)号：US20230307541A1

    公开(公告)日：2023-09-28

    申请号：US17702593

    申请日：2022-03-23

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand S. Murthy ,  Pushkar Sharad Ranade ,  Sagar Suthram

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

    CPC classification number: H01L29/78391 ,  H01L29/42364 ,  H01L29/516 ,  H01L29/6684

    Abstract: Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include thick hysteretic elements (i.e., hysteretic elements having a thickness of at least 10-15 nanometers, e.g., between 55 and 100 nanometers), and related methods and devices. Transistor gate stacks disclosed herein include a multilayer gate insulator having a thick hysteretic element and an interface layer, where the thick hysteretic element is between the interface layer and a gate electrode material, and the interface layer is between the thick hysteretic element and a channel material of a transistor. The interface layer may be a dielectric material with an effective dielectric constant of at least 20 and/or be a dielectric material that is thinner than about 3 nanometers. Such an interface layer may help improve gate control and allow use of thick hysteretic elements while maintaining transistor performance in terms of, e.g., gate leakage, carrier mobility, and subthreshold swing.

    PARTIAL GATE CUT STRUCTURES IN AN INTEGRATED CIRCUIT
    32.
    发明公开
    PARTIAL GATE CUT STRUCTURES IN AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20230299135A1

    公开(公告)日：2023-09-21

    申请号：US17697129

    申请日：2022-03-17

    Applicant: Intel Corporation

    Inventor： Leonard P. Guler ,  Tahir Ghani ,  Saurabh Morarka ,  Charles H. Wallace

    IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L27/088

    CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/6656 ,  H01L27/0886

    Abstract: Techniques are provided herein to form an integrated circuit having any number of partial gate cut structures between adjacent semiconductor devices. Neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. In some such examples, a partial gate cut structure is present between a given pair of neighboring semiconductor devices. The partial gate cut structure acts as a dielectric pillar between the semiconductor structures that allows the conductive gate layer (from the gate structure) to extend above and/or below it such that the gates of each of the semiconductor devices remain electrically coupled together. The gate cut structure itself removes a portion of the gate layer from between the semiconductor devices, thus reducing parasitic capacitance.

    INTEGRATED CIRCUIT DEVICES WITH ANGLED TRANSISTORS FORMED BASED ON ANGLED WAFERS
    36.
    发明公开
    INTEGRATED CIRCUIT DEVICES WITH ANGLED TRANSISTORS FORMED BASED ON ANGLED WAFERS 审中-公开

    公开(公告)号：US20230268382A1

    公开(公告)日：2023-08-24

    申请号：US17677239

    申请日：2022-02-22

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Wilfred Gomes ,  Sagar Suthram

    IPC: H01L29/04 ,  H01L29/06 ,  H01L29/66

    CPC classification number: H01L29/045 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/42392

    Abstract: IC devices including angled transistors formed based on angled wafers are disclosed. An example IC device includes a substrate and a semiconductor structure. A crystal direction of a crystal structure in the semiconductor structure is not aligned with a corresponding crystal direction (e.g., having same Miller indices) of a crystal structure in the substrate. An angle between the two crystal directions may be 4-60 degrees. The semiconductor structure is formed based on another substrate (e.g., a wafer) that has a different orientation from the substrate, e.g., flats or notches of the two substrates are not aligned. The crystal direction of the semiconductor structure may be determined based on a crystal direction in the another substrate. The semiconductor structure may be a portion of a transistor, e.g., the channel region and S/D regions of the transistor. The semiconductor structure may be angled with respect to an edge of the substrate.

    SRAM WITH NANORIBBON WIDTH MODULATION FOR GREATER READ STABILITY
    38.
    发明公开
    SRAM WITH NANORIBBON WIDTH MODULATION FOR GREATER READ STABILITY 审中-公开

    公开(公告)号：US20230209797A1

    公开(公告)日：2023-06-29

    申请号：US17560779

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Clifford Ong ,  Leonard Guler ,  Smita Shridharan ,  Zheng Guo ,  Eric Karl ,  Tahir Ghani

    IPC: H01L27/11

    CPC classification number: H01L27/1108

    Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.

Patent Agency Ranking