公开(公告)号：US20060163729A1

公开(公告)日：2006-07-27

申请号：US11389717

申请日：2006-03-27

申请人： Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

发明人： Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3128 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/17517 ,  H01L2224/81136 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2224/05099

摘要： A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

摘要翻译： 提供了一种新的方法和封装，用于安装已经提供有小间距输入/输出互连凸块的半导体器件。 由柱状金属和焊料凸点组成的细间距焊料凸块直接施加到半导体器件的I / O焊盘，然后将器件倒装芯片接合到基板上。 可以为设备的I / O焊盘布置以便需要对器件的附加机械支撑的情况下提供虚拟凸块。

公开(公告)号：US20060163714A1

公开(公告)日：2006-07-27

申请号：US11030097

申请日：2005-01-07

申请人： Pei-Haw Tsao ,  Chender Huang ,  Chuen-Jye Lin

发明人： Pei-Haw Tsao ,  Chender Huang ,  Chuen-Jye Lin

IPC分类号： H01L23/24

CPC分类号： H01L23/4334 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.

公开(公告)号：US20100068846A1

公开(公告)日：2010-03-18

申请号：US12591071

申请日：2009-11-06

申请人： Pei-Haw Tsao ,  Chender Huang ,  Chuen-Jye Lin

发明人： Pei-Haw Tsao ,  Chender Huang ,  Chuen-Jye Lin

IPC分类号： H01L31/18

CPC分类号： H01L23/4334 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.

摘要翻译： 一种封装结构及其制造方法。 该结构包括具有端子的衬底，覆盖衬底的芯片，具有活性表面的芯片，具有中心区域和外围区域，外围区域具有电极，图案化盖板覆盖芯片并暴露电极， 电连接电极和端子的导电材料以及覆盖端子，导电材料和电极的密封剂，但是覆盖在芯片的中心区域上的盖板。

公开(公告)号：US07638887B2

公开(公告)日：2009-12-29

申请号：US11030097

申请日：2005-01-07

申请人： Pei-Haw Tsao ,  Chender Huang ,  Chuen-Jye Lin

发明人： Pei-Haw Tsao ,  Chender Huang ,  Chuen-Jye Lin

IPC分类号： H01L23/28

CPC分类号： H01L23/4334 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.

摘要翻译： 一种封装结构及其制造方法。 该结构包括具有端子的衬底，覆盖衬底的芯片，具有活性表面的芯片，具有中心区域和外围区域，外围区域具有电极，图案化盖板，覆盖芯片并暴露电极， 电连接电极和端子的导电材料以及覆盖端子，导电材料和电极的密封剂，但是覆盖在芯片的中心区域上的盖板。

公开(公告)号：US20090267213A1

公开(公告)日：2009-10-29

申请号：US12384977

申请日：2009-04-09

申请人： Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

发明人： Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

IPC分类号： H01L23/488 ,  H01L23/18

CPC分类号： H01L23/49816 ,  H01L24/06 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/06136 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

摘要翻译： 提供了一种新的方法和封装，用于安装已经提供有小间距输入/输出互连凸块的半导体器件。 由柱状金属和焊料凸点组成的细间距焊料凸块直接施加到半导体器件的I / O焊盘，然后将器件倒装芯片接合到基板上。 可以为设备的I / O焊盘布置以便需要对器件的附加机械支撑的情况下提供虚拟凸块。

公开(公告)号：US20060103006A1

公开(公告)日：2006-05-18

申请号：US10988100

申请日：2004-11-12

申请人： Chao-Yuan Su ,  Chen-Der Huang ,  Pei-Haw Tsao ,  Chuen-Jye Lin

发明人： Chao-Yuan Su ,  Chen-Der Huang ,  Pei-Haw Tsao ,  Chuen-Jye Lin

IPC分类号： H01L23/06

CPC分类号： H05K1/0271 ,  H01L23/13 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K2201/0187 ,  H05K2201/068 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/0401

摘要： A substrate design to improve chip package reliability is provided. The chip package includes a substrate having a ceramic layer formed in a recess. A die is attached to the substrate on the ceramic layer. The substrate may be attached to a printed circuit board. The substrate may be fabricated by forming a recess in a substrate, such as a multi-layer substrate formed of organic dielectric materials. A ceramic layer is then affixed to the substrate in the recess. A die may be attached to the ceramic layer and the substrate may be attached to a printed circuit board.