公开(公告)号：US09812367B2

公开(公告)日：2017-11-07

申请号：US14621440

申请日：2015-02-13

申请人： Ju-Youn Kim ,  Ji-Hwan An ,  Kwang-Yul Lee ,  Tae-Won Ha ,  Jeong-Nam Han

发明人： Ju-Youn Kim ,  Ji-Hwan An ,  Kwang-Yul Lee ,  Tae-Won Ha ,  Jeong-Nam Han

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L21/82345 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/823431 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795

摘要： A method of fabricating a semiconductor device includes forming an inter-metal dielectric layer including a first trench and a second trench which are spaced from each other on a substrate, forming a first dielectric layer along the sides and bottom of the first trench, forming a second dielectric layer along the sides and bottom of the second trench, forming first and second lower conductive layers on the first and second dielectric layers, respectively, forming first and second capping layers on the first and second lower conductive layer, respectively, performing a heat treatment after the first and second capping layers have been formed, removing the first and second capping layers and the first and second lower conductive layers after performing the heat treatment, and forming first and second metal gate structures on the first and second dielectric layers, respectively.

公开(公告)号：US09054210B2

公开(公告)日：2015-06-09

申请号：US13479679

申请日：2012-05-24

申请人： Sang-Jine Park ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Kee-Sang Kwon ,  Won-Sang Choi

发明人： Sang-Jine Park ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Kee-Sang Kwon ,  Won-Sang Choi

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/02 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L21/823425 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/78

摘要： A method of fabricating a semiconductor device, the method including forming on a substrate a transistor that includes a gate electrode and a source and drain region, forming an interlayer insulating film on the transistor, forming a contact hole in the interlayer insulating film to expose a top surface of the source and drain region, and a thin film is formed at an interface between the contact hole and the exposed top surface of the source and drain region. The method further including selectively removing at least a portion of the thin film by performing an etching process in a non-plasma atmosphere, forming an ohmic contact film on the source and drain region where at least a portion of the thin film was selectively removed, and forming a contact plug by filling the contact hole with a conductive material.

摘要翻译： 一种制造半导体器件的方法，所述方法包括在衬底上形成包括栅极和源极和漏极区的晶体管，在所述晶体管上形成层间绝缘膜，在所述层间绝缘膜中形成接触孔以暴露出 源极和漏极区域的顶表面，并且在接触孔和源极和漏极区域的暴露顶表面之间的界面处形成薄膜。 该方法还包括通过在非等离子体气氛中进行蚀刻工艺来选择性地去除薄膜的至少一部分，在选择性地去除薄膜的至少一部分的源区和漏区上形成欧姆接触膜， 以及通过用导电材料填充接触孔来形成接触塞。

公开(公告)号：US08673724B2

公开(公告)日：2014-03-18

申请号：US13561245

申请日：2012-07-30

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/78 ,  H01L29/7848

摘要： Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.

摘要翻译： 提供制造半导体器件的方法，其包括提供包括具有栅极图案的第一区域和具有填充第一沟槽的第一沟槽和绝缘层的第二区域的衬底。 通过蚀刻绝缘层的一部分露出第一沟槽的侧壁的一部分，并且在栅极图案的侧壁上形成第一间隔物。 第二间隔件形成在第一沟槽的暴露的侧壁上，其中第一间隔件和第二间隔件同时形成。

公开(公告)号：US08652915B2

公开(公告)日：2014-02-18

申请号：US13212380

申请日：2011-08-18

申请人： Kevin Ahn ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Jeong-Nam Han

发明人： Kevin Ahn ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/336

CPC分类号： H01L21/02532 ,  H01L21/0262 ,  H01L21/3083 ,  H01L29/66545 ,  H01L29/66636

摘要： A method of fabricating a semiconductor device can be provided by etching sidewalls of a preliminary trench in a substrate that are between immediately adjacent gate electrode structures, to recess the sidewalls further beneath the gate electrode structures to provide recessed sidewalls. Then, the recessed sidewalls and a bottom of the preliminary trench can be etched using crystallographic anisotropic etching to form a hexagonally shaped trench in the substrate.

摘要翻译： 半导体器件的制造方法可以通过蚀刻位于紧邻的栅电极结构之间的衬底中的预备沟槽的侧壁，从而在栅极电极结构之下进一步凹入侧壁以提供凹入的侧壁。 然后，可以使用晶体各向异性蚀刻来蚀刻预备沟槽的凹陷侧壁和底部，以在衬底中形成六边形形状的沟槽。

公开(公告)号：US20130115759A1

公开(公告)日：2013-05-09

申请号：US13561245

申请日：2012-07-30

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/20

CPC分类号： H01L29/66636 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/78 ,  H01L29/7848

摘要： Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.

摘要翻译： 提供制造半导体器件的方法，其包括提供包括具有栅极图案的第一区域和具有填充第一沟槽的第一沟槽和绝缘层的第二区域的衬底。 通过蚀刻绝缘层的一部分露出第一沟槽的侧壁的一部分，并且在栅极图案的侧壁上形成第一间隔物。 第二间隔件形成在第一沟槽的暴露的侧壁上，其中第一间隔件和第二间隔件同时形成。

公开(公告)号：US20120309189A1

公开(公告)日：2012-12-06

申请号：US13444175

申请日：2012-04-11

申请人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Yoon-Hae Kim ,  Doo-Sung Yun

发明人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Yoon-Hae Kim ,  Doo-Sung Yun

IPC分类号： H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76877

摘要： In a method for fabricating a semiconductor device, a semiconductor device is provided including an interlayer dielectric film and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric film through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric film and the first and second hard mask patterns to fill the first trench. First and second hard mask trimming patterns are formed by trimming sidewalls of the first and second hard mask patterns and removing the filler material to expose the first trench. A damascene wire is formed by filling the first trench with a conductive material.

摘要翻译： 在制造半导体器件的方法中，提供了半导体器件，其包括层间绝缘膜和顺序堆叠在其上的第一和第二硬掩模图案。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间电介质膜中。 在层间电介质膜和第一和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过修剪第一和第二硬掩模图案的侧壁并去除填充材料以暴露第一沟槽而形成第一和第二硬掩模修剪图案。 通过用导电材料填充第一沟槽来形成镶嵌线。

公开(公告)号：US20120104514A1

公开(公告)日：2012-05-03

申请号：US13241324

申请日：2011-09-23

申请人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Myung-Geun Song

发明人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Myung-Geun Song

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

摘要： Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

摘要翻译： 提供一种可以促进自对准硅化物工艺并且可以防止栅极由于不对准而被损坏的半导体器件，以及半导体器件的制造方法。 该方法包括在具有形成在栅极图案的两侧的栅极图案和源极/漏极区域的衬底上形成第一绝缘层图案，第一绝缘层图案具有源极/漏极区域的暴露部分，形成硅化物 在所述暴露的源极/漏极区上形成第二绝缘层，以在所述衬底的整个表面上形成覆盖所述第一绝缘层图案和所述硅化物层的第二绝缘层，以及在所述第二绝缘层中形成接触孔以露出所述硅化物层。

公开(公告)号：US20120049250A1

公开(公告)日：2012-03-01

申请号：US13191055

申请日：2011-07-26

申请人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Jae-Jik Baek ,  Byung-Kwon Cho

发明人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Jae-Jik Baek ,  Byung-Kwon Cho

IPC分类号： H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor integrated circuit device includes a substrate. A gate structure is formed on the substrate and includes a gate insulating film and a gate electrode. A first sidewall spacer is formed on two sidewalls of the gate structure. A second sidewall spacer is formed on the first sidewall spacer. A recess compensation film is interposed between the second sidewall spacer and the substrate. An epitaxial layer is in contact with the recess compensation film.

摘要翻译： 半导体集成电路器件包括衬底。 栅极结构形成在衬底上并且包括栅极绝缘膜和栅电极。 第一侧壁间隔件形成在栅极结构的两个侧壁上。 在第一侧壁间隔件上形成第二侧壁间隔物。 在第二侧壁间隔件和基板之间设置凹陷补偿膜。 外延层与凹部补偿膜接触。

公开(公告)号：US09443979B2

公开(公告)日：2016-09-13

申请号：US14455036

申请日：2014-08-08

申请人： Sang-Jine Park ,  Bo-Un Yoon ,  Ha-Young Jeon ,  Byung-Kwon Cho ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Bo-Un Yoon ,  Ha-Young Jeon ,  Byung-Kwon Cho ,  Jeong-Nam Han

IPC分类号： H01L29/78 ,  H01L27/08 ,  H01L21/28 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC分类号： H01L29/66545 ,  H01L21/28114 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.

摘要翻译： 半导体器件包括限定沟槽的栅极间隔。 沟槽包括顺序地位于基板上的第一部分和第二部分。 第一部分的内表面具有锐角的斜面，并且第二部分的内表面具有相对于基底的直角或钝角的斜率。 栅电极填充沟槽的至少一部分。

公开(公告)号：US08404580B2

公开(公告)日：2013-03-26

申请号：US13444175

申请日：2012-04-11

申请人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Yoon-Hae Kim ,  Doo-Sung Yun

发明人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Yoon-Hae Kim ,  Doo-Sung Yun

IPC分类号： H01L21/4763

CPC分类号： H01L21/31144 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76877

摘要： In a method for fabricating a semiconductor device, a semiconductor device is provided including an interlayer dielectric film and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric film through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric film and the first and second hard mask patterns to fill the first trench. First and second hard mask trimming patterns are formed by trimming sidewalls of the first and second hard mask patterns and removing the filler material to expose the first trench. A damascene wire is formed by filling the first trench with a conductive material.

摘要翻译： 在制造半导体器件的方法中，提供了半导体器件，其包括层间绝缘膜和顺序堆叠在其上的第一和第二硬掩模图案。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间电介质膜中。 在层间电介质膜和第一和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过修剪第一和第二硬掩模图案的侧壁并去除填充材料以暴露第一沟槽而形成第一和第二硬掩模修剪图案。 通过用导电材料填充第一沟槽来形成镶嵌线。