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公开(公告)号：US20100320563A1
公开(公告)日：2010-12-23
申请号：US12870921
申请日：2010-08-30
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/76807 , H01L21/76892 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element.
摘要翻译： 一个结构。 该结构包括：基底; 衬底中的第一电极; 在所述基板和所述电极的顶部上的介电层; 在所述第一介电层上的第二电介质层，所述第二电介质层包括第二电介质材料; 埋入第一介电层中的熔丝元件，其中熔融元件（i）物理分离，（ii）与二者直接物理接触，（iii）被夹在介电层的第一区域和第二区域之间; 以及在所述熔丝元件的顶部上的第二电极，其中所述第一电极和所述第二电极通过所述熔丝元件彼此电耦合。
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32.发明授权Dielectric material with reduced dielectric constant and methods of manufacturing the same 失效具有降低介电常数的介电材料及其制造方法公开(公告)号：US07732322B2
公开(公告)日：2010-06-08
申请号：US11360350
申请日：2006-02-23
IPC分类号： H01L21/4763
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/02238 , H01L21/02252 , H01L21/31633 , H01L21/7682 , H01L21/76831
摘要： In a first aspect, a first method of manufacturing a dielectric material with a reduced dielectric constant is provided. The first method includes the steps of (1) forming a dielectric material layer including a trench on a substrate; and (2) forming a cladding region in the dielectric material layer by forming a plurality of air gaps in the dielectric material layer along at least one of a sidewall and a bottom of the trench so as to reduce an effective dielectric constant of the dielectric material. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了制造介电常数降低的介电材料的第一种方法。 第一种方法包括以下步骤：（1）在衬底上形成包括沟槽的电介质材料层; 以及（2）通过沿着沟槽的侧壁和底部中的至少一个形成电介质材料层中的多个气隙，从而在电介质材料层中形成包层区域，从而降低电介质材料的有效介电常数 。 提供了许多其他方面。
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33.发明授权Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures 有权具有封装的栅电极的半导体FinFET结构和用于形成这种半导体FinFET结构的方法公开(公告)号：US07384838B2
公开(公告)日：2008-06-10
申请号：US11225654
申请日：2005-09-13
IPC分类号： H01L21/8238
CPC分类号： H01L29/785 , H01L29/66795
摘要： Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated from the process that dopes the fin body to form the source/drain regions. The sidewalls of the gate electrode are covered by sidewall spacers that are formed on the gate electrode but not on the sidewall of the fin body.
摘要翻译： 其中FinFET的栅极被从引入掺杂剂的工艺掩模到FinFET的鳍状体中以形成源极/漏极区域的半导体结构以及制造这种半导体结构的方法。 栅极掺杂以及因此栅电极的功函数有利地与掺杂鳍体以形成源极/漏极区的过程隔离。 栅电极的侧壁由形成在栅电极上但不在鳍体的侧壁上的侧壁间隔物覆盖。
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公开(公告)号：US06552378B1
公开(公告)日：2003-04-22
申请号：US09385931
申请日：1999-08-30
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10832 , H01L27/10873
摘要： A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transfer device formed in a substantially electrically isolated mesa region extending over a substantial arc of the outer perimeter of the trench, a buried strap which conductively connects the transfer device to the storage capacitor, wherein the transfer device has a controlled conduction channel located at a position of the arc removed from the buried strap.
摘要翻译： 本文公开了一种具有4.5F2或更小尺寸的半导体存储器单元的制造结构和方法，其中F是最小光刻尺寸。 半导体存储单元包括形成在沟槽中的存储电容器，形成在基本上电隔离的台面区域中的转移装置，该台面区域延伸在沟槽的外周边的大致圆弧上，将传输装置导电地连接到存储电容器 ，其中所述传送装置具有位于从所述掩埋带移除的所述弧的位置处的受控传导通道。
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公开(公告)号：US06512275B1
公开(公告)日：2003-01-28
申请号：US09473908
申请日：1999-12-28
IPC分类号： H01L27088
CPC分类号： H01L29/785 , H01L27/088 , H01L27/092 , Y10S257/90
摘要： A semiconductor apparatus and method for making the same is disclosed herein in which the semiconductor apparatus includes a first active device formed in a mesa region of semiconductor material formed on one or more sidewalls of an isolation region, and a conductive path which extends from the active device in a linear direction of the mesa. An embodiment is disclosed in which a plurality of active devices are formed in the mesa region and electrically connected thereby.
摘要翻译： 本发明公开了半导体装置及其制造方法，其中半导体装置包括形成在隔离区的一个或多个侧壁上形成的半导体材料的台面区域中的第一有源器件，以及从该有源器件延伸的导电路径 装置在台面的线性方向。 公开了一种实施例，其中在台面区域中形成多个有源器件并由此电连接。
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36.发明授权Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure 有权用于形成在一个衬底上包括NVRAM，DRAM和/或SRAM存储器结构的存储器结构的工艺以及用于形成新的NVRAM单元结构的工艺公开(公告)号：US06232173B1
公开(公告)日：2001-05-15
申请号：US09159470
申请日：1998-09-23
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , G11C11/005 , H01L27/105 , H01L27/10808 , H01L27/10852 , H01L27/115 , H01L27/11517 , H01L27/11526
摘要： A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure, and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same substrate. An NVRAM cell structure. Processes for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and processes for forming a new NVRAM cell structure.
摘要翻译： 一种包括NVRAM单元结构，DRAM单元结构和SRAM单元结构的半导体存储器件。 NVRAM单元结构，DRAM单元结构和SRAM单元结构位于相同的基板上。 NVRAM单元结构。 用于形成在一个衬底上包括NVRAM，DRAM和/或SRAM存储器结构并且用于形成新的NVRAM单元结构的处理的存储器结构的过程。
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公开(公告)号：US6069390A
公开(公告)日：2000-05-30
申请号：US7906
申请日：1998-01-15
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/088 , H01L27/092
CPC分类号： H01L29/785 , H01L27/088 , H01L27/092 , Y10S257/90
摘要： A semiconductor apparatus and method for making the same is disclosed herein in which the semiconductor apparatus includes a first active device formed in a mesa region of semiconductor material formed on one or more sidewalls of an isolation region, and a conductive path which extends from the active device in a linear direction of the mesa. An embodiment is disclosed in which a plurality of active devices are formed in the mesa region and electrically connected thereby.
摘要翻译： 本发明公开了半导体装置及其制造方法，其中半导体装置包括形成在隔离区的一个或多个侧壁上形成的半导体材料的台面区域中的第一有源器件，以及从该有源器件延伸的导电路径 装置在台面的线性方向。 公开了一种实施例，其中在台面区域中形成多个有源器件并由此电连接。
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38.发明授权Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure 失效低成本混合内存集成结构，新的NVRAM结构，以及形成混合内存和NVRAM结构的过程
公开(公告)号：US5880991A
公开(公告)日：1999-03-09
申请号：US824702
申请日：1997-04-14
IPC分类号： G11C11/00 , H01L21/8242 , H01L21/8244 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： H01L27/10894 , G11C11/005 , H01L27/105 , H01L27/10808 , H01L27/115 , H01L27/11517 , H01L27/11526 , H01L27/10852
摘要： A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure, and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same substrate. An NVRAM cell structure. Processes for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and processes for forming a new NVRAM cell structure.
摘要翻译： 一种包括NVRAM单元结构，DRAM单元结构和SRAM单元结构的半导体存储器件。 NVRAM单元结构，DRAM单元结构和SRAM单元结构位于相同的基板上。 NVRAM单元结构。 用于形成在一个衬底上包括NVRAM，DRAM和/或SRAM存储器结构并且用于形成新的NVRAM单元结构的处理的存储器结构的过程。
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公开(公告)号：US5689127A
公开(公告)日：1997-11-18
申请号：US610949
申请日：1996-03-05
IPC分类号： H01L21/8238 , H01L21/336 , H01L27/092 , H01L29/78 , H01L29/786 , H01L29/76 , H01L29/94
CPC分类号： H01L29/66666 , H01L29/7827 , H01L29/78612 , H01L29/78642
摘要： A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.
摘要翻译： 垂直双栅极场效应晶体管包括在体或SOI衬底上排列成堆叠的源极层，外延沟道层和漏极层。 栅极氧化物使用差分氧化速率在堆叠的侧面热生长以最小化输入电容问题。 栅极围绕堆叠的一端缠绕，而在第二端形成触点。 嵌入堆叠的第二端的蚀刻停止层使得能够直接与沟道层进行接触。
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40.发明授权Dielectric material with a reduced dielectric constant and methods of manufacturing the same 失效具有降低的介电常数的介电材料及其制造方法公开(公告)号：US07948084B2
公开(公告)日：2011-05-24
申请号：US11928913
申请日：2007-10-30
IPC分类号： H01L23/48
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/02238 , H01L21/02252 , H01L21/31633 , H01L21/7682 , H01L21/76831
摘要： In a first aspect, a first method of manufacturing a dielectric material with a reduced dielectric constant is provided. The first method includes the steps of (1) forming a dielectric material layer including a trench on a substrate; and (2) forming a cladding region in the dielectric material layer by forming a plurality of air gaps in the dielectric material layer along at least one of a sidewall and a bottom of the trench so as to reduce an effective dielectric constant of the dielectric material. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了制造介电常数降低的介电材料的第一种方法。 第一种方法包括以下步骤：（1）在衬底上形成包括沟槽的电介质材料层; 以及（2）通过沿着沟槽的侧壁和底部中的至少一个形成电介质材料层中的多个气隙，从而在电介质材料层中形成包层区域，从而降低电介质材料的有效介电常数 。 提供了许多其他方面。
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