公开(公告)号：US20060024906A1

公开(公告)日：2006-02-02

申请号：US11116190

申请日：2005-04-28

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21/20

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7687 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/40

Abstract: The present invention provides a semiconductor device, having: a semiconductor substrate; a first electrode formed over the semiconductor substrate; a first insulation film covering the first electrode and having an aperture for exposing a part of the first electrode; a first conductive film formed on a part of the first insulation film and the first electrode inside the aperture; an isolation region placed inside the aperture; and a second conductive film formed on the first conductive film and the isolation region.

Abstract translation: 本发明提供一种半导体器件，具有：半导体衬底; 形成在半导体衬底上的第一电极; 覆盖所述第一电极并具有用于暴露所述第一电极的一部分的孔的第一绝缘膜; 形成在第一绝缘膜的一部分上的第一导电膜和孔内的第一电极; 放置在孔内的隔离区; 以及形成在第一导电膜和隔离区上的第二导电膜。

公开(公告)号：US20050212612A1

公开(公告)日：2005-09-29

申请号：US11039872

申请日：2005-01-24

Applicant: Takashi Kawakubo ,  Ryoichi Ohara ,  Kazuhide Abe ,  Hiroshi Yoshida ,  Hiroshi Tsurumi

Inventor： Takashi Kawakubo ,  Ryoichi Ohara ,  Kazuhide Abe ,  Hiroshi Yoshida ,  Hiroshi Tsurumi

IPC: H01G7/06 ,  H03B5/00 ,  H03H7/075 ,  H03H7/12 ,  H03H9/00 ,  H03H9/17 ,  H03H9/46 ,  H03H9/54 ,  H03H9/58 ,  H03H9/60 ,  H03H9/64 ,  H03H11/04 ,  H03J1/00 ,  H03J3/08

CPC classification number: H03J3/08 ,  H03H9/542 ,  H03H9/605 ,  H03H2210/012 ,  H03H2210/015 ,  H03J1/0008

Abstract: A tunable filter has a plurality of variable capacitors and a plurality of inductor elements, each being formed on a common substrate, a filter circuit formed by using at least a portion of the plurality of variable capacitors and a portion of the plurality of inductor elements, a monitor circuit formed by using at least a portion of the plurality of variable capacitors and a portion of the plurality of inductor elements, a detecting circuit which detects a prescribed circuit constant of the monitor circuit, a storage which stores information relating to a reference circuit constant of the monitor circuit, and a capacitance control circuit which controls capacitance of the variable capacitors in the monitor circuit and capacitance of the variable capacitors in the filter circuit, based on a result detected by the detecting circuit and information stored in the storage.

Abstract translation: 可调谐滤波器具有多个可变电容器和多个电感器元件，每个电感器元件形成在公共基板上，通过使用多个可变电容器的至少一部分和多个电感器元件的一部分形成的滤波器电路， 通过使用多个可变电容器的至少一部分和多个电感器元件的一部分形成的监视电路，检测监视电路的规定电路常数的检测电路，存储与参考电路有关的信息的存储器 基于由检测电路检测的结果和存储在存储器中的信息，控制监视电路中的可变电容器的电容和滤波器电路中的可变电容器的电容的电容控制电路。

公开(公告)号：US20050194867A1

公开(公告)日：2005-09-08

申请号：US11054404

申请日：2005-02-10

Applicant: Takashi Kawakubo ,  Ryoichi Ohara ,  Tomio Ono ,  Toshihiko Nagano ,  Michihiko Nishigaki ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Kenya Sano

Inventor： Takashi Kawakubo ,  Ryoichi Ohara ,  Tomio Ono ,  Toshihiko Nagano ,  Michihiko Nishigaki ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Kenya Sano

IPC: H01L41/09 ,  H01G7/06 ,  H01L41/053 ,  H01L41/08 ,  H01L41/18 ,  H01L41/187 ,  H01L41/22 ,  H01L41/29 ,  H01L41/316

CPC classification number: H01G7/06 ,  H01H2057/006 ,  H01L41/0933 ,  H01L41/094

Abstract: A thin film piezoelectric actuator comprises a driving part at least one end of which is supported by an anchor portion. The driving part includes: a piezoelectric film, a first lower electrode provided under a first region of the piezoelectric film, a second lower electrode provided under a second region different from the first region of the piezoelectric film, a first upper electrode provided opposite to the first lower electrode on the piezoelectric film, a second upper electrode provided opposite to the second lower electrode on the piezoelectric film, a first connection part that electrically connects the first lower electrode and the second upper electrode via a first via hole formed in the piezoelectric film, and a second connection part that electrically connects the second lower electrode and the first upper electrode via a second via hole formed in the piezoelectric film.

Abstract translation: 薄膜压电致动器包括驱动部件，其至少一端由锚固部分支撑。 驱动部包括：压电膜，设置在压电膜的第一区域下方的第一下电极，设置在与压电膜的第一区不同的第二区域下方的第二下电极，与第一下电极相对设置的第一上电极 压电膜上的第一下电极，与压电膜上的第二下电极相对设置的第二上电极，经由形成在压电膜中的第一通孔电连接第一下电极和第二上电极的第一连接部 以及第二连接部，其经由形成在所述压电膜中的第二通路孔电连接所述第二下部电极和所述第一上部电极。

公开(公告)号：US20050009319A1

公开(公告)日：2005-01-13

申请号：US10765155

申请日：2004-01-28

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21/3205 ,  H01L21/302 ,  H01L21/304 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/7685 ,  H01L21/7684 ,  H01L21/76867

Abstract: A method of forming buried wiring, includes the steps of forming an insulating layer having a trench on a semiconductor substrate; forming a conductive layer mainly composed of copper on the insulating layer in such a manner that the trench is filled with the conductive layer; removing an oxide layer generated in a surface of the conductive layer by oxidation; forming a cap layer made of a material having less mechanical strength than the oxide layer, on the conductive layer; and removing the cap layer and a part of the conductive layer by chemical mechanical polishing in such a manner that the conductive layer is left in the trench.

公开(公告)号：US06797957B2

公开(公告)日：2004-09-28

申请号：US10097405

申请日：2002-03-15

Applicant: Takashi Kawakubo ,  Kazuhide Abe ,  Kenya Sano

Inventor： Takashi Kawakubo ,  Kazuhide Abe ,  Kenya Sano

IPC: H01L3702

CPC classification number: H01L37/02

Abstract: An infrared detection element having a single-crystalline base layer 3 with a thickness of 50 nm to 10 &mgr;m having a principal surface, a first electrode layer 4 formed on the principal surface of the single-crystalline base layer 3, a ferroelectric layer 5 which is formed on the first electrode layer 4 and is composed of a single-crystalline layer or a unidirectionally oriented layer. Distortion of the single-crystalline layer or a unidirectionally oriented layer in a surface parallel to the principal surface of the single-crystalline base layer 3 is elastically constrained by the single-crystalline base layer 3. The infrared detection element further has a second electrode layer 6 formed on the ferroelectric layer 5. An amount of charge varies with changes in temperature caused by irradiation of infrared light to the ferroelectric layer 5.

Abstract translation: 具有厚度为50nm〜10μm的具有主面的单晶基底层3的红外线检测元件，形成在单晶基底层3的主面上的第一电极层4，强电介质层5 形成在第一电极层4上，由单晶层或单向取向层构成。 在与单晶基底层3的主表面平行的表面中的单晶层或单向取向层的失真由单晶基底层3弹性约束。红外线检测元件还具有第二电极层 形成在铁电层5上。电荷量随着红外光照射到铁电层5而引起的温度变化。

公开(公告)号：US06533906B2

公开(公告)日：2003-03-18

申请号：US09795479

申请日：2001-03-01

Applicant: Takashi Kawakubo ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Naoko Yanase

Inventor： Takashi Kawakubo ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Naoko Yanase

IPC: C23C1434

CPC classification number: C23C14/345 ,  C23C14/0068 ,  C23C14/088 ,  C23C14/3407 ,  C23C14/352 ,  C30B23/02 ,  C30B29/22 ,  C30B29/32 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/31691 ,  H01L28/55

Abstract: A method of manufacturing an epitaxially-strained lattice film of an oxide, in which epitaxially-strained lattices having a good crystalline property are formed by applying RF power to a substrate holder and irradiating positive ions having a moderate energy while preventing damage to the strained lattice film to be stacked by oxygen negative ions. This method simultaneously overcomes both the problem of damage to the film by irradiation of oxygen negative ions, which is peculiar to sputtering of oxides, and the problem of failure to strain due to relaxation of the strain during deposition.

Abstract translation: 制造具有良好结晶特性的外延应变晶格的氧化物的外延应变晶格膜的方法通过向衬底保持器施加RF功率并照射具有中等能量的正离子而形成，同时防止对应变晶格的损伤 膜由氧负离子堆叠。 该方法同时克服了通过照射氧负离子（这是氧化物溅射所特有的）对膜的损坏的问题，以及由于沉积期间的应变松弛而导致的不能应变的问题。

公开(公告)号：US06455430B2

公开(公告)日：2002-09-24

申请号：US09431181

申请日：1999-11-01

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21302

CPC classification number: H01L21/76802 ,  H01L21/3146 ,  H01L21/3212 ,  H01L21/7684

Abstract: A carbon film is formed over an insulating film and a contact hole is defined therein by patterning. Copper is formed over an entire surface including the contact hole and polished by chemical mechanical polishing. The polishing of the copper is terminated with the carbon film as an etching stopper thereby to allow the copper to remain in the contact hole alone, whereby an embedded interconnection made up of the copper is formed by a damascene method.

Abstract translation: 在绝缘膜上形成碳膜，通过图案化形成接触孔。 铜在包括接触孔的整个表面上形成并通过化学机械抛光抛光。 用碳膜作为蚀刻停止器终止铜的抛光，从而允许铜单独留在接触孔中，由此通过镶嵌法形成由铜构成的嵌入式互连。

公开(公告)号：US6103618A

公开(公告)日：2000-08-15

申请号：US346943

申请日：1999-07-02

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76859 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76885

Abstract: A method for forming an interconnection in a semiconductor element includes a process for forming a groove on an underlying substrate so as to correspond to the designed pattern of the interconnection. An underlayer for improving crystalline orientation of the interconnection is formed on the underlying substrate having the groove. A thin film of interconnection material is formed in the groove and a heattreatment process is carried out to ensure that the groove is filled with the thin film of the interconnection material. Formation of the interconnection is completed by polishing the surface of the thin film by a predetermined quantity.

Abstract translation: 在半导体元件中形成互连的方法包括在下面的基底上形成与所设计的互连图案对应的凹槽的工艺。 用于改善互连结晶取向的底层形成在具有凹槽的底层基底上。 在槽中形成互连材料的薄膜，并进行热处理工艺，以确保槽被互连材料的薄膜填充。 通过以预定量抛光薄膜的表面来完成互连的形成。

公开(公告)号：US5889299A

公开(公告)日：1999-03-30

申请号：US804394

申请日：1997-02-21

Applicant: Kazuhide Abe ,  Shuichi Komatsu ,  Mitsuaki Izuha ,  Noburu Fukushima ,  Kenya Sano ,  Takashi Kawakubo

Inventor： Kazuhide Abe ,  Shuichi Komatsu ,  Mitsuaki Izuha ,  Noburu Fukushima ,  Kenya Sano ,  Takashi Kawakubo

IPC: H01L21/02 ,  H01L29/76

CPC classification number: H01L28/55

Abstract: A thin film capacitor including a first electrode having on its surface a (100) face of cubic system or a (001) face of tetragonal system, a dielectric thin film epitaxially grown on the first electrode and exhibiting a crystal structure which inherently belongs to a perovskite structure of cubic system, and a second electrode formed on the dielectric thin film. Further, the dielectric thin film meets the following relationship V/V.sub.0 .gtoreq.1.01 where a unit lattice volume of true perovskite crystal structure belonging to the cubic system (lattice constant a.sub.0) is represented by V.sub.0 =a.sub.0.sup.3, and a unit lattice volume (lattice constant a=b.noteq.c) which is strained toward a tetragonal system after the epitaxial growth is represented by V=a.sup.2 c, and also meets the following relationship c/a.gtoreq.1.01 where c/a represents a ratio between a lattice constant "c" in the direction thicknesswise of the film and a lattice constant "a" in the direction parallel with a plane of the film.

Abstract translation: 一种薄膜电容器，包括在其表面上具有立方体系的（100）面或四方晶系的（001）面的第一电极，在第一电极上外延生长并呈现出固有地属于 立方体的钙钛矿结构，以及形成在电介质薄膜上的第二电极。 此外，电介质薄膜满足以下关系V / V0 / = 1.01，其中属于立方体系的真实钙钛矿晶体结构的单位晶格体积（晶格常数a0）由V0 = a03表示，单位晶格体积 晶格常数a = b NOTEQUAL c），其外延生长后由V = a2c表示为四方晶系，并满足以下关系c / a> / = 1.01其中c / a表示晶格常数 在膜的厚度方向上的“c”和与膜的平面平行的方向上的晶格常数“a”。

公开(公告)号：US5670808A

公开(公告)日：1997-09-23

申请号：US591153

申请日：1996-01-25

Applicant: Kazuya Nishihori ,  Yoshiaki Kitaura ,  Yoshikazu Tanabe ,  Tomonori Aoyama ,  Kyoichi Suguro ,  Kumi Okuwada ,  Shuichi Komatsu ,  Kazuhide Abe

Inventor： Kazuya Nishihori ,  Yoshiaki Kitaura ,  Yoshikazu Tanabe ,  Tomonori Aoyama ,  Kyoichi Suguro ,  Kumi Okuwada ,  Shuichi Komatsu ,  Kazuhide Abe

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/095 ,  H01L29/92 ,  H01L27/108

CPC classification number: H01L27/0629 ,  H01L27/0605 ,  H01L27/10852 ,  H01L28/40

Abstract: A semiconductor device in which an SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 um) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.

Abstract translation: 其中SiO 2膜和第一布线层依次布置在GaAs衬底上的半导体器件。 在第一布线层上形成电容器。 电容器包括从下侧依次具有由Ti层，Mo层和Pt层构成的多层结构的下电极。 电容器还包括由钛酸锶制成的电介质膜。 电容器还包括从下侧依次具有由WNx层（120μm）和W层（300nm）组成的多层结构的上部电极。 与电介质膜接触的上电极的表面由氮化钨层限定。