公开(公告)号：US06265907B1

公开(公告)日：2001-07-24

申请号：US09053365

申请日：1998-04-01

申请人： Shunichi Sukegawa

发明人： Shunichi Sukegawa

IPC分类号： H03L522

CPC分类号： G11C7/065 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078

摘要： A signal transmission circuit which enables the distance of signal transmission to be increased, while the signal delay and power consumption are reduced. The signal transmission circuit includes a driver circuit, a receiver circuit, an equalizer circuit that flattens the output of the driver circuit, and an intermediate amplifier circuit. The intermediate amplifier circuit is connected to input/output shared terminals in the wiring that connects the driver circuit and the receiver circuit. With the aid of the positive feedback of the intermediate amplifier circuit, a differential signal output from the driver circuit is amplified and then transmitted to the receiver circuit.

摘要翻译： 信号传输电路能够在信号延迟和功耗降低的同时增加信号传输的距离。 信号传输电路包括驱动电路，接收器电路，使驱动电路的输出变平的均衡器电路和中间放大器电路。 中间放大器电路连接到连接驱动电路和接收电路的布线中的输入/输出共用端子。 借助于中间放大器电路的正反馈，从驱动电路输出的差分信号被放大然后传输到接收器电路。

公开(公告)号：US6002162A

公开(公告)日：1999-12-14

申请号：US90721

申请日：1998-06-04

申请人： Yasushi Takahashi ,  Tsutomu Takahashi ,  Koji Arai ,  Shinji Bessho ,  Shunichi Sukegawa ,  Masayuki Hira

发明人： Yasushi Takahashi ,  Tsutomu Takahashi ,  Koji Arai ,  Shinji Bessho ,  Shunichi Sukegawa ,  Masayuki Hira

IPC分类号： H01L21/8242 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  H01L27/108 ,  H01L29/72

CPC分类号： H01L27/10897 ,  G11C11/4074

摘要： Realizing a reduction of the layout surface area by rendering unnecessary the region used for well isolation. In this DRAM, a triple well construction is used, and all of the regions for the unit memory cell array MA, the word line driver bank WDB, the sense amplifier bank SAB, and the cross area CR are surrounded by a lower layer N-type deep (deep layer) well 12. A back bias VPP corresponding to the power supply voltage of the word line driver is applied to the N well 14, and a back bias VBB corresponding to the characteristics of the memory cell are applied to the P well 16. In the N well 14, in regard to the P-type MOS transistors of the sense amplifier that undergo the substrate bias effect due to the back bias VPP, the threshold voltage is set to a low value so as to cancel that bias effect. Also, in the P well 16, in regard to the N-type MOS transistors of the sense amplifiers that undergo the substrate bias effect due to the back bias VBB, the threshold voltage is designed to a low value so as to cancel that bias effect.

摘要翻译： 通过使用于隔离的区域不必要地实现布局表面积的减小。 在该DRAM中，使用三阱结构，并且用于单位存储单元阵列MA，字线驱动器组WDB，读出放大器组SAB和交叉区域CR的所有区域被下层N- 类型深（深层）阱12.对应于字线驱动器的电源电压的背偏压VPP被施加到N阱14，并且对应于存储器单元的特性的反偏压VBB被施加到P 在N阱14中，关于由于反偏压VPP而经历衬底偏置效应的读出放大器的P型MOS晶体管，阈值电压被设置为低值，以抵消该偏置 影响。 此外，在P阱16中，关于由于背偏压VBB而经历衬底偏置效应的读出放大器的N型MOS晶体管，阈值电压被设计为低值，以抵消该偏置效应 。

公开(公告)号：US5970010A

公开(公告)日：1999-10-19

申请号：US116915

申请日：1998-07-17

申请人： Masayuki Hira ,  Shunichi Sukegawa ,  Shinji Bessho ,  Yasushi Takahashi ,  Koji Arai ,  Tsutomu Takahashi ,  Tsugio Takahashi

发明人： Masayuki Hira ,  Shunichi Sukegawa ,  Shinji Bessho ,  Yasushi Takahashi ,  Koji Arai ,  Tsutomu Takahashi ,  Tsugio Takahashi

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/401 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： Controlling the timing for the overdrive of the sense amplifiers in response to the wiring length between the sense amplifiers and the power supply voltage supply nodes, and designing a reduction of the power consumption by preventing excessive overdrive of the bit lines.The supply timing for the power supply voltage to each sense amplifier bank is controlled according to the wiring length between the supply nodes CT0, CT1, CT2 for the power supply used for the driving of the sense amplifiers and each sense amplifier bank SB0 to SB16, and since the supply time for the overdrive voltage to the sense amplifier bank SB0 at the near end is set short and the supply time for the overdrive voltage is set successively longer as it goes towards the far end, the sensing delay that originates in the voltage drop that is generated in the wiring between the supply nodes and the sense amplifier banks is compensated for, uniformity of the overdrive for the bit lines at both the far and near ends can be achieved, the excessive overdrive at the sense amplifier bank (memory cell mat) at the near end can be avoided, and by extension, a reduction of the power consumption can be realized.

摘要翻译： 响应于读出放大器和电源电压节点之间的布线长度来控制感测放大器的过驱动的定时，以及通过防止位线的过度过载来设计功耗的降低。 根据用于驱动读出放大器和每个读出放大器组SB0至SB16的电源的供电节点CT0，CT1，CT2之间的布线长度，控制每个感测放大器组的电源电压的供应定时， 并且由于将近端的读出放大器组SB0的过驱动电压的供给时间设定得较短，并且对于过驱动电压的供给时间随着朝向远端而连续设定，所以产生于电压的感测延迟 在供电节点和感测放大器组之间的布线中产生的下降被补偿，可以实现在远端和近端的位线的过驱动的均匀性，在感测放大器组（存储单元）处的过度过驱动 垫）可以避免，并且通过扩展，可以实现功率消耗的降低。

公开(公告)号：US5862086A

公开(公告)日：1999-01-19

申请号：US701348

申请日：1996-08-22

申请人： Chisa Makimura ,  Yukihide Suzuki ,  Shunichi Sukegawa ,  Hiroyuki Fujiwara ,  Masayuki Hira

发明人： Chisa Makimura ,  Yukihide Suzuki ,  Shunichi Sukegawa ,  Hiroyuki Fujiwara ,  Masayuki Hira

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/804 ,  G11C29/808

摘要： A semiconductor storage device is provided with a storage circuit for a faulty address and a plurality of redundant word lines corresponding to the storage circuit. The storage circuit is adapted to store a faulty address required for selecting a redundant word line. The faulty address is compared with an address input at the time of memory access by a comparator. Using a coincidence signal produced from the comparator and a predetermined address signal contained in the input address, a defect relief circuit selects one of the redundant word lines in place of the faulty word line.

摘要翻译： 半导体存储装置具有用于故障地址的存储电路和对应于存储电路的多个冗余字线。 存储电路适于存储选择冗余字线所需的故障地址。 故障地址与比较器存储器访问时的地址输入进行比较。 使用从比较器产生的符合信号和包含在输入地址中的预定地址信号，缺陷消除电路选择一个冗余字线来代替有缺陷的字线。

公开(公告)号：US5485425A

公开(公告)日：1996-01-16

申请号：US375727

申请日：1995-01-20

申请人： Hidetoshi Iwai ,  Masaya Muranaka ,  Takumi Nasu ,  Shunichi Sukegawa

发明人： Hidetoshi Iwai ,  Masaya Muranaka ,  Takumi Nasu ,  Shunichi Sukegawa

IPC分类号： G11C11/401 ,  G11C17/12 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C17/126 ,  G11C29/84

摘要： There is provided a semiconductor memory device having a redundant column. This memory device has a redundant column disposed in the direction of the Y-system address, a ROM accessed by using an X-system address, a Y-system address signal having a defective cell included in the cells therein being electrically written into the ROM, a comparator circuit for comparing a signal read out from this ROM with a Y-system address signal and outputting a coincidence signal upon coincidence, and a defect relieving circuit responsive to output of the coincidence signal from this comparator circuit to cause selection of the redundant column of Y system instead of the Y-system address selection device.

摘要翻译： 提供了具有冗余列的半导体存储器件。 该存储装置具有沿Y系统地址的方向设置的冗余列，通过使用X系统地址访问的ROM，其中包含在其中的单元中的具有缺陷单元的Y系统地址信号被电写入ROM 比较电路，用于将从该ROM读出的信号与Y系统地址信号进行比较，并且一致地输出一致信号，以及响应来自该比较器电路的符合信号的输出的缺陷消除电路，以选择冗余 Y系列的列，而不是Y系统地址选择设备。

公开(公告)号：US5103113A

公开(公告)日：1992-04-07

申请号：US537554

申请日：1990-06-13

申请人： Takashi Inui ,  Shunichi Sukegawa

发明人： Takashi Inui ,  Shunichi Sukegawa

IPC分类号： G06F1/025 ,  H03K19/013

CPC分类号： H03K19/013 ,  G06F1/025

摘要： A driving circuit for providing a predetermined voltage as a driving signal to a respective word line in a dynamic random access memory in a short time. The driving circuit includes an operation signal supply circuit portion for providing an operation signal, a driving signal output circuit portion which receives the operation signal and provides a driving signal as an output, and a voltage supply circuit portion for providing a predetermined voltage to the driving signal output circuit portion in producing the driving signal. A bipolar switching element is provided in the driving signal output circuit portion to control the voltage supply from the voltage supply circuit portion and responds to the operation signal to provide the voltage from the voltage supply circuit portion as the voltage producing the driving signal in a short time.

摘要翻译： 一种用于在短时间内向动态随机存取存储器中的相应字线提供预定电压作为驱动信号的驱动电路。 驱动电路包括用于提供操作信号的操作信号供给电路部分，接收操作信号并提供驱动信号作为输出的驱动信号输出电路部分和用于向驱动提供预定电压的电压供应电路部分 信号输出电路部分产生驱动信号。 双极开关元件设置在驱动信号输出电路部分中，以控制来自电压供应电路部分的电压供应，并响应于操作信号，以提供来自电压供应电路部分的电压作为短路产生驱动信号 时间。

公开(公告)号：US5021852A

公开(公告)日：1991-06-04

申请号：US353858

申请日：1989-05-18

申请人： Shunichi Sukegawa ,  Takashi Inui

发明人： Shunichi Sukegawa ,  Takashi Inui

IPC分类号： H01L27/06 ,  H01L27/108

CPC分类号： H01L27/10829 ,  H01L27/0623

摘要： This invention relates to a semiconductor integrated circuit device which has an insulated-gate type element part comprising a capacitor which is formed through the use of a trench in a semiconductor layer, wherein a low-resistance buried layer is formed in the semiconductor layer prior to forming the trench so that the trench is formed to be surrounded by the low-resistance buried layer and thereby the low-resistance buried layer is used as an electrode of the capacitor.

摘要翻译： 本发明涉及具有绝缘栅型元件的半导体集成电路器件，该绝缘栅型元件包括通过使用半导体层中的沟槽形成的电容器，其中在半导体层之前形成低电阻掩埋层 形成沟槽，使得沟槽形成为被低电阻掩埋层包围，从而将低电阻掩埋层用作电容器的电极。

公开(公告)号：US08541878B2

公开(公告)日：2013-09-24

申请号：US13050338

申请日：2011-03-17

申请人： Hiroshi Takahashi ,  Shunichi Sukegawa ,  Keishi Inoue

发明人： Hiroshi Takahashi ,  Shunichi Sukegawa ,  Keishi Inoue

IPC分类号： H01L23/485

CPC分类号： H01L27/14634 ,  H01L21/76802 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/535 ,  H01L24/05 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14638 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/1469 ,  H01L31/02002 ,  H01L31/02008 ,  H01L31/02013 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/08145 ,  H01L2224/24147 ,  H01L2224/48463 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

公开(公告)号：US20110233702A1

公开(公告)日：2011-09-29

申请号：US13050338

申请日：2011-03-17

申请人： Hiroshi Takahashi ,  Shunichi Sukegawa ,  Keishi Inoue

发明人： Hiroshi Takahashi ,  Shunichi Sukegawa ,  Keishi Inoue

IPC分类号： H01L31/0232 ,  H01L31/18 ,  H01L27/14

CPC分类号： H01L27/14634 ,  H01L21/76802 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/535 ,  H01L24/05 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14638 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/1469 ,  H01L31/02002 ,  H01L31/02008 ,  H01L31/02013 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/08145 ,  H01L2224/24147 ,  H01L2224/48463 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

摘要翻译： 一种半导体器件，包括与第二材料层相邻的第一材料层，穿过第一材料层并延伸到第二材料层中的第一通孔，以及延伸到第一材料层中的第二通孔，沿着共同的截面平行 到两个材料层之间的界面，第一通孔具有大于第二通孔的横截面。

公开(公告)号：US6038158A

公开(公告)日：2000-03-14

申请号：US189071

申请日：1998-11-09

申请人： Shinji Bessho ,  Shunichi Sukegawa ,  Masayuki Hira ,  Yasushi Takahashi ,  Tsutomu Takahashi ,  Kohji Arai

发明人： Shinji Bessho ,  Shunichi Sukegawa ,  Masayuki Hira ,  Yasushi Takahashi ,  Tsutomu Takahashi ,  Kohji Arai

IPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/18 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/02 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C7/18

摘要： The objective is to realize a semiconductor memory capable of avoiding an increase in the load of the sense amplifiers, easily realizing a large capacity and high integration of the memory, reducing the current consumption by the bit lines, and improving the access speed. Because the levels of the selection signal lines SHUS1, SHUE1, SHDS1, and SHDE1 are set by the control circuit, only one of the aforementioned four selection signal lines is selected at the time of memory access, other selection signal lines are held in unselect status, and the sense amplifiers in the sense amplifier bank SB1a and prescribed bit line pairs or extended bit line pairs are connected to each other by response in order to carry out read or write; thus, the load of the sense amplifiers can be reduced, and high speed, large capacity, and high integration can be achieved.

摘要翻译： 目的是实现能够避免读出放大器的负载增加的半导体存储器，容易实现存储器的大容量和高集成度，减少位线的电流消耗，并提高存取速度。 由于选择信号线SHUS1，SHUE1，SHDS1和SHDE1的电平由控制电路设置，所以在存储器访问时仅选择上述四个选择信号线中的一个，其他选择信号线保持在取消选择状态 并且读出放大器组SB1a中的读出放大器和规定的位线对或扩展位线对通过响应彼此连接以便执行读或写; 因此能够降低读出放大器的负担，能够实现高速，大容量，高集成度。