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55 条记录 (耗时 0.023 秒)

    Dynamic RAM
    2.
    发明授权
    Dynamic RAM 失效
    动态RAM

    公开(公告)号：US08068379B1

    公开(公告)日：2011-11-29

    申请号：US09050946

    申请日：1998-03-31

    申请人： Tsutomu Takahashi ,  Kouji Arai ,  Yasushi Takahashi ,  Atsuya Tanaka ,  Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira

    发明人： Tsutomu Takahashi ,  Kouji Arai ,  Yasushi Takahashi ,  Atsuya Tanaka ,  Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira

    IPC分类号： G11C8/00

    CPC分类号： H01L27/0207 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4097 ,  H01L27/10891

    摘要： A plurality of sub word lines each have a length equivalent to the division of a main word line along the extension direction thereof, arranged along a bit line crossing said main word line, and are connected with a plurality of memory cells. A first sub word select line arranged in parallel to the main word line is extended to a plurality of sub arrays arranged in the extension direction of the word line. A second sub word select line is connected to the corresponding one of said first sub word select line to be extended orthogonally to a word line driving circuit area of an adjacent sub array. In the sub word line driving circuit provided for each sub array, a sub word line is selected and deselected by signals supplied from said main word line and said second sub word select line.

    摘要翻译： 多个子字线各自具有与沿着其延伸方向的主字线的划分相等的长度，沿着与所述主字线交叉的位线布置，并且与多个存储单元连接。 与主字线平行布置的第一子字选择线被扩展到沿字线的延伸方向布置的多个子阵列。 第二子字选择线连接到所述第一子字选择线中的相应一个，以与正交相邻子阵列的字线驱动电路区域正交延伸。 在为每个子阵列提供的子字线驱动电路中，通过从所述主字线和所述第二子字选择线提供的信号来选择和取消副字线。

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07012831B2

    公开(公告)日：2006-03-14

    申请号：US10749559

    申请日：2004-01-02

    申请人： Kenichi Shigenami ,  Shunichi Sukegawa

    发明人： Kenichi Shigenami ,  Shunichi Sukegawa

    IPC分类号： G11C11/24

    CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/4076

    摘要： A semiconductor memory device for realizing high speed writing while maintaining the credibility of write data, wherein a write gate is provided between a bit line and an input/output data line of a memory cell array, the write gate becomes open when a selected word line becomes an activation state and a write signal set to the input/output data line in accordance with write data is applied to the selected bit line via the write gate when writing, so that writing of data to a selected memory cell can be performed immediately after activating the selected word line when writing, and writing to the selected memory cell can be performed in parallel with reading and refreshing of non-selected memory cells, and consequently, a time for storing charges to the selected memory cell can be sufficiently secured and writing at a high speed can be realized.

    摘要翻译： 一种用于在保持写入数据的可信度的同时实现高速写入的半导体存储器件，其中在存储单元阵列的位线和输入/输出数据线之间提供写入门，当选择的字线 成为激活状态，并且根据写数据设置到输入/输出数据线的写入信号在写入时经由写入门被施加到所选择的位线，使得可以在之后立即执行到所选择的存储器单元的写入 在写入时激活所选择的字线，并且可以与未选择的存储单元的读取和刷新并行地执行对所选择的存储器单元的写入，因此可以充分确保用于存储对所选存储单元的电荷的时间和写入 可以实现高速度。

    Semiconductor memory device having a back gate voltage controlled delay circuit
    7.
    发明授权
    Semiconductor memory device having a back gate voltage controlled delay circuit 有权
    具有背栅电压控制延迟电路的半导体存储器件

    公开(公告)号：US6034920A

    公开(公告)日：2000-03-07

    申请号：US198816

    申请日：1998-11-24

    申请人： Shunichi Sukegawa ,  Shinji Bessho ,  Tadashi Tachibana ,  Hiroyuki Yoshida

    发明人： Shunichi Sukegawa ,  Shinji Bessho ,  Tadashi Tachibana ,  Hiroyuki Yoshida

    IPC分类号： G11C7/06 ,  G11C8/18 ,  G11C8/00

    CPC分类号： G11C8/18 ,  G11C7/06

    摘要： A semiconductor memory device has an address buffer (200, 230). A pre-decoder circuit (202, 232) receives the output of the address buffer (200, 230), and a memory array (212) receives the output of the pre-decoder circuit. A main amplifier (216, 248) in turn receives the output of the memory array (212, 244). An address transition detector (ATD) pulse generator circuit (204, 234) also receives the output of the address buffer (200, 230), and a pulse delay circuit (208, 240) receives the output of the address transition detector pulse generator circuit (204, 234). The pulse delay circuit (208, 240) also provides a main amplifier signal to the main amplifier (216, 248). The memory device further includes a voltage generator (206, 236) that generates a back gate voltage which is provided as a low voltage supply (V.sub.BB) for the address transition detector (ATD) pulse generator circuit (204, 234) and the pulse delay circuit (208, 240). The address transition detector (ATD) pulse generator (204, 234) and the pulse delay circuit (208, 240) have a delay that is controlled by the back gate voltage (V.sub.BB) and has a reduced dependency on a high voltage supply (V.sub.DD) of the memory device.

    摘要翻译： 半导体存储器件具有地址缓冲器（200,230）。 预解码器电路（202,232）接收地址缓冲器（200,230）的输出，存储器阵列（212）接收预解码器电路的输出。 主放大器（216,248）又接收存储器阵列（212,244）的输出。 地址转换检测器（ATD）脉冲发生器电路（204,234）还接收地址缓冲器（200,230）的输出，并且脉冲延迟电路（208,240）接收地址转换检测器脉冲发生器电路的输出 （204,234）。 脉冲延迟电路（208,240）还向主放大器（216,248）提供主放大器信号。 存储装置还包括产生背栅电压的电压发生器（206,236），该栅极电压作为用于地址转换检测器（ATD）脉冲发生器电路（204,234）的低电压电源（VBB）和脉冲延迟 电路（208,240）。 地址转换检测器（ATD）脉冲发生器（204,234）和脉冲延迟电路（208,240）具有由背栅极电压（VBB）控制的延迟，并且对高电压源（VDD）的依赖性降低 ）的存储器件。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5768214A

    公开(公告)日：1998-06-16

    申请号：US689548

    申请日：1996-08-09

    申请人： Ken Saitoh ,  Shunichi Sukegawa ,  Tadashi Tachibana ,  Makoto Saeki ,  Yukihide Suzuki

    发明人： Ken Saitoh ,  Shunichi Sukegawa ,  Tadashi Tachibana ,  Makoto Saeki ,  Yukihide Suzuki

    IPC分类号： G11C11/41 ,  G11C7/06 ,  G11C8/18 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C8/18 ,  G11C7/06

    摘要： A semiconductor memory device in which erroneous operation with respect to undesired level changes of the input address signal is prevented, and appropriate operation of the main amplifier is ensured. The semiconductor memory device has a main amplifier activating pulse generator 112' which includes response sensitivity reduction circuit 10, response sensitivity selector 12, and main amplifier activating pulse generator 14. The response sensitivity reduction circuit 10 can reduce the response sensitivity or input sensitivity of the circuit 112' with respect to an input address transition detection pulse ATD. The response sensitivity selector 12 selects either a first input terminal A1 or a second input terminal A2, depending on the output state of the main amplifier activating pulse generator 14. Consequently, when there is no output of a main amplifier activating pulse MA from the main amplifier activating pulse generator 14, the response sensitivity selector 12 switches to first input terminal A1 to select response sensitivity reduction circuit 10; when a main amplifier activating pulse MA is output, the selector 12 switches to second input terminal A2 to select bypass circuit 11.

    摘要翻译： 一种半导体存储器件，其中防止了与输入地址信号的不期望的电平变化有关的错误操作，并且确保了主放大器的适当的操作。 半导体存储器件具有主放大器激活脉冲发生器112'，其包括响应灵敏度降低电路10，响应灵敏度选择器12和主放大器激活脉冲发生器14.响应灵敏度降低电路10可以降低响应灵敏度降低电路10的响应灵敏度或输入灵敏度 电路112'相对于输入地址转换检测脉冲ATD。 响应灵敏度选择器12根据主放大器激活脉冲发生器14的输出状态选择第一输入端子A1或第二输入端子A2。因此，当没有主放大器从主振荡器激活脉冲MA的输出 放大器激活脉冲发生器14，响应灵敏度选择器12切换到第一输入端子A1以选择响应灵敏度降低电路10; 当输出主放大器激活脉冲MA时，选择器12切换到第二输入端A2以选择旁路电路11。