公开(公告)号：US20140056072A1

公开(公告)日：2014-02-27

申请号：US14066450

申请日：2013-10-29

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung

IPC: G11C16/04

CPC classification number: G11C16/04 ,  G11C16/0483 ,  H01L23/5225 ,  H01L27/11578 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines.

Abstract translation: 存储器件包括具有多个电平的存储器单元块。 每个级别包括在块的第一和第二端之间沿第一方向延伸的存储器单元条。 在第一端的每个级别处的第一位线结构耦合到从第一端延伸的第一串存储器单元。 在第二端的每个级别处的第二位线结构耦合到从所述第二端延伸的第二存储单元串。 位线对在第一个方向上延伸，每个包括奇数和偶数位线。 奇偶位线连接器将奇数位和偶数位线分别连接到第二和第一位线结构。 一系列位线对的每个位线由相邻位线对的位线分开。

公开(公告)号：US12014798B2

公开(公告)日：2024-06-18

申请号：US17710367

申请日：2022-03-31

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Shuo-Nan Hung

IPC: G11C7/10

CPC classification number: G11C7/1057 ,  G11C7/1069 ,  G11C7/1084 ,  G11C7/1096

Abstract: A compute in memory device comprises a memory array including a plurality of data lines for parallel access to memory array data, and an input/output interface. Data path circuits between the memory array and the input/output interface include a page buffer, each buffer cell of the page buffer including a plurality of storage elements. A plurality of computation circuits is provided connected to respective buffer cells. The computation circuits execute a function of data in the storage elements of the respective buffer cells and can be configured in parallel to generate a results data page including operation results for the plurality of buffer cells. A data analysis circuit is connected to the data path circuits to execute a function of the results data page to generate an analysis result. A register can be provided to store the analysis result accessible via the input/output interface.

公开(公告)号：US11734181B2

公开(公告)日：2023-08-22

申请号：US17579428

申请日：2022-01-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung ,  Chun-Lien Su

IPC: G06F12/08 ,  G06F12/0882

CPC classification number: G06F12/0882 ,  G06F2212/1024 ,  G06F2212/2022

Abstract: A memory device includes a data register operatively coupled to the memory array, a cache operatively coupled to the data register, and an input/output interface operatively coupled to the cache. A controller executes a continuous page read operation to sequentially load pages to the data register and move the pages to the cache, in response to a page read command, executes the cache read operation in response to a cache read command to move data from the cache to the input/output interface, and to stall moving of the data from the cache until a next cache read command, and terminates the continuous page read operation in response to a terminate command.

公开(公告)号：US20220137842A1

公开(公告)日：2022-05-05

申请号：US17089972

申请日：2020-11-05

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung ,  E-Yuan Chang

IPC: G06F3/06

Abstract: A memory controller accesses a memory page in a memory block of a storage memory array of a memory device. The memory controller reads memory data stored in the accessed memory page. The memory controller determines a number of error bits associated with the memory data. The memory controller obtains an erase count corresponding to the accessed memory page, the erase count indicating a number of erase operations performed on the accessed memory page. The memory controller determines, from among one or more error threshold values, an error threshold value based at least on the erase count. The memory controller determines a relationship between the number of error bits and the error threshold value. The memory controller triggers a data refresh for the accessed memory block if the relationship between the number of error bits and the error threshold value satisfy a known criterion.

公开(公告)号：US11049585B1

公开(公告)日：2021-06-29

申请号：US16832983

申请日：2020-03-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G11C29/00 ,  G11C29/44 ,  G11C11/409 ,  G11C29/26

Abstract: Field configurable bad block repair for a memory array comprising a plurality of blocks utilizes a block repair information store for data identifying one or more bad blocks in the array. The block repair information store includes nonvolatile memory writable at least once. Block repair circuitry on the device is configurable to redirect commands to access bad blocks identified in the bad block repair information store to reserved blocks in the memory array. A controller is responsive to a command to write bad block repair information, such as an identifier of a bad block in the plurality of blocks to the block repair information store in the field, and to reconfigure the block repair circuitry in the field using the updated information.

公开(公告)号：US09805803B2

公开(公告)日：2017-10-31

申请号：US14471769

申请日：2014-08-28

Applicant: MACRONIX International Co., Ltd.

Inventor： Shuo-Nan Hung ,  Shin-Jang Shen ,  Wei-Jen Chen

IPC: G11C16/14 ,  G11C16/08

CPC classification number: G11C16/14 ,  G11C16/08

Abstract: A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, an adjustment unit, and a switch. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate. The switch is coupled in series with the adjustment unit between the select gate and the well.

公开(公告)号：US09478314B2

公开(公告)日：2016-10-25

申请号：US14486963

申请日：2014-09-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hungwei Lu ,  Wei-An Lai ,  Shuo-Nan Hung ,  Chi Lo

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C16/00 ,  G11C29/04

CPC classification number: G11C29/42 ,  G11C16/00 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411

Abstract: An integrated circuit memory includes a memory array, including a plurality of data lines. A buffer structure is coupled to the plurality of data lines, including a plurality of storage elements to store bit-level status values for the plurality of data lines. The memory includes logic to indicate bundle-level status values of corresponding bundles of storage elements in the buffer structure based on the bit-level status values of bits in the corresponding bundles. A plurality of bundle status circuits is arranged in a daisy chain and coupled to respective bundles in the buffer structure, producing an output of the daisy chain indicating detection of a bundle in the first status. Control circuitry executes cycles to determine the output of the daisy chain, each cycle clearing a bundle status circuit indicating the first status if the output indicates detection of a bundle in the first status in the cycle.

Abstract translation: 集成电路存储器包括包括多条数据线的存储器阵列。 缓冲结构耦合到多条数据线，包括多个存储元件以存储多条数据线的位级状态值。 存储器包括基于相应束中的位的位级状态值来指示缓冲器结构中的对应的存储元件束的束级状态值的逻辑。 多个束状态电路被布置在菊花链中并且耦合到缓冲器结构中的各个束，从而产生指示在第一状态下检测束的菊花链的输出。 控制电路执行周期以确定菊花链的输出，每个周期清除捆绑状态电路，指示第一状态，如果输出指示在周期中处于第一状态的捆绑检测。

公开(公告)号：US20160064086A1

公开(公告)日：2016-03-03

申请号：US14471769

申请日：2014-08-28

Applicant: MACRONIX International Co., Ltd.

Inventor： Shuo-Nan Hung ,  Shin-Jang Shen ,  Wei-Jen Chen

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C16/08

Abstract: A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, an adjustment unit, and a switch. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate. The switch is coupled in series with the adjustment unit between the select gate and the well.

Abstract translation: 提供了用于调整非易失性存储器的选择栅极电压的电路。 电路包括井，选择门，调节单元和开关。 井与选择门之间存在电容耦合。 调整单元产生用于选择门的驱动电压。 开关与选择门和井之间的调节单元串联耦合。

公开(公告)号：US20140254284A1

公开(公告)日：2014-09-11

申请号：US14046428

申请日：2013-10-04

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Ti Wen Chen ,  Shuo-Nan Hung ,  Shih-Lin Huang

IPC: G11C16/16

CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/12

Abstract: A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage.

Abstract translation: 存储器电路包括耦合到存储器阵列的字线，包括在擦除操作中取消选择的一个或多个字线的第一组以及在擦除操作中选择的一个或多个字线的第二组。 响应于接收到擦除操作的擦除命令，控制电路将擦除操作中未选择的一个或多个字线的第一组耦合到参考电压。 一些示例还包括可将字线可切换地耦合到全局字线的第一晶体管，以及可切换地将字线耦合到接地电压的第二晶体管。 控制电路耦合到第一晶体管和第二晶体管，其中控制电路具有包括至少擦除操作的多个模式。 在第一模式中，第一晶体管将字线耦合到全局字线，并且第二晶体管将字线与接地电压分离。 在第二模式中，第一晶体管将字线与全局字线分离，并且第二晶体管将字线耦合到接地电压。

公开(公告)号：US08760928B2

公开(公告)日：2014-06-24

申请号：US13710992

申请日：2012-12-11

Applicant: Macronix International Co., Ltd

Inventor： Ti-Wen Chen ,  Hang-Ting Lue ,  Shuo-Nan Hung ,  Shih-Lin Huang ,  Chih-Chang Hsieh ,  Kuo-Pin Chang

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  G11C11/56 ,  G11C5/14

CPC classification number: G11C16/26 ,  G11C5/146 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/1157

Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.

Abstract translation: 电荷存储存储器配置在NAND阵列中，并且包括经由串选择开关耦合到位线的NAND串并且包括字线。 控制器被配置为产生用于对NAND阵列的所选单元执行操作的偏置。 该偏置包括在字符串选择开关闭合时对位线进行充电，例如不会将这种位线充电引起的噪声引入串中。 在耦合到所选字线的NAND串中的存储器单元的两侧的存储单元中的半导体主体区域被耦合到参考电压，使得它们被预充电，而阵列中的字符串的字线 在操作期间转变为各种电压。