公开(公告)号：US10297611B1

公开(公告)日：2019-05-21

申请号：US15903307

申请日：2018-02-23

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Luan C. Tran ,  Jie Li ,  Anish A. Khandekar ,  Kunal Shrotri

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/10 ,  H01L29/06 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L21/02

Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

公开(公告)号：US10163685B2

公开(公告)日：2018-12-25

申请号：US15684080

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/764 ,  H01L21/20 ,  H01L21/02

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US10153197B2

公开(公告)日：2018-12-11

申请号：US15684728

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/764 ,  H01L21/20 ,  H01L21/02

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US10026643B2

公开(公告)日：2018-07-17

申请号：US15687509

申请日：2017-08-27

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/00 ,  H01L21/764 ,  H01L21/20 ,  H01L21/02

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US20180019157A1

公开(公告)日：2018-01-18

申请号：US15684612

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/764 ,  H01L21/02 ,  H01L21/20

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US20170352578A1

公开(公告)日：2017-12-07

申请号：US15684728

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/764 ,  H01L21/02 ,  H01L21/20

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US20160260664A1

公开(公告)日：2016-09-08

申请号：US15150734

申请日：2016-05-10

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Gurtej S. Sandhu

IPC: H01L23/528 ,  H01L29/167 ,  H01L21/3205 ,  H01L21/306 ,  H01L21/223 ,  H01L23/532 ,  H01L29/04

CPC classification number: H01L23/528 ,  H01L21/2236 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/743 ,  H01L21/761 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/84 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/53271 ,  H01L27/1027 ,  H01L27/1203 ,  H01L27/2472 ,  H01L29/04 ,  H01L29/06 ,  H01L29/167 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.

Abstract translation: 公开了包括设置在介电材料的轨道之间的半导体材料的主体的半导体结构的形成方法。 这种方法可以包括用介电材料填充衬底中的多个沟槽，并且去除介电材料之间的衬底的部分以形成多个开口。 在一些实施例中，衬底的部分可以被底切以在主体下面形成连续的空隙，并且连续的空隙可以用导电材料填充。 在其他实施例中，暴露在开口内的基板的部分可以转化为硅化物材料，以在主体下面形成导电材料。 例如，导电材料可以用作导电线以电连接存储器件部件。 还公开了通过这些方法形成的半导体结构和器件。

公开(公告)号：US09117744B2

公开(公告)日：2015-08-25

申请号：US13971169

申请日：2013-08-20

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/20 ,  H01L21/02

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract translation: 一些实施例包括在半导体结构内形成空隙的方法。 在一些实施例中，空隙可以用作用于分配冷却剂的微结构，用于引导电磁辐射，或用于材料的分离和/或表征。 一些实施例包括其中具有对应于空隙，导管，绝缘结构，半导体结构或导电结构的微结构的结构。

公开(公告)号：US20150235699A1

公开(公告)日：2015-08-20

申请号：US14702330

申请日：2015-05-01

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Jun Liu

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C5/02 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0054

Abstract: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

Abstract translation: 存储器件包括多个存储器单元，每个存储器单元包括存储元件和选择器件。 多个第一（例如，行）地址线可以在多个的至少一些单元的第一侧相邻（例如，在下方）。 多个第二（例如，列）地址线跨越多个行地址线延伸，每个列地址线在至少一些单元的第二相对侧相邻（例如，在上）。 控制电路可以被配置为基本上同时向地址线施加读取电压或写入电压。 还公开了包括这种存储器件的系统和至少基本上同时访问多个单元的方法。

公开(公告)号：US20150137214A1

公开(公告)日：2015-05-21

申请号：US14606415

申请日：2015-01-27

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  David H. Wells ,  Tuman E. Allen

IPC: H01L29/792 ,  H01L21/762 ,  H01L29/16 ,  H01L21/28 ,  H01L29/06 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/792 ,  H01L21/02532 ,  H01L21/28282 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/1027 ,  H01L27/10802 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

Abstract translation: 半导体结构包括与下面的衬底间隔开的半导体材料的主体。 物体可以通过介电材料，开放体积和导电材料中的至少一种与基底物理分离。 主体可以通过一个或多个导电结构电耦合，其可以用作互连结构以电耦合存储器件的部件。 通过在主体之间提供隔离，半导体结构提供常规SOI衬底（例如，高速度，低功率，增加的器件密度和隔离）的性质，同时显着减少与这种SOI衬底相关联的制造动作和成本。 另外，本公开的半导体结构由于通过中间介电材料隔离物体而提供减小的寄生耦合和电流泄漏。