公开(公告)号：US20230017305A1

公开(公告)日：2023-01-19

申请号：US17730325

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Mattia Cichocki ,  Vladimir Mikhalev ,  Phani Bharadwaj Vanguri ,  James Eric Davis ,  Kenneth William Marr ,  Chiara Cerafogli ,  Michael James Irwin ,  Domenico Tuzi ,  Umberto Siciliani ,  Alessandro Alilla ,  Andrea Giovanni Xotta ,  Chung-Ping Wu ,  Luigi Marchese ,  Pasquale Conenna ,  Joonwoo Nam ,  Ishani Bhatt ,  Fulvio Rori ,  Andrea D'Alessandro ,  Michele Piccardi ,  Aleksey Prozapas ,  Luigi Pilolli ,  Violante Moschiano

IPC: H01L27/02 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A variety of applications can include apparatus or methods that provide a well ring for resistive ground power domain segregation. The well ring can be implemented as a n-well in a p-type substrate. Resistive separation between ground domains can be generated by biasing a n-well ring to an external supply voltage. This approach can provide a procedure, from a process standpoint, that provides relatively high flexibility to design for chip floor planning and simulation, while providing sufficient noise rejection between independent ground power domains when correctly sized. Significant noise rejection between ground power domains can be attained.

公开(公告)号：US20220130476A1

公开(公告)日：2022-04-28

申请号：US17519676

申请日：2021-11-05

Applicant: Micron Technology, Inc.

Inventor： Fulvio Rori ,  Chiara Cerafogli

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/32 ,  G11C16/16

Abstract: An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

公开(公告)号：US11276461B1

公开(公告)日：2022-03-15

申请号：US17108897

申请日：2020-12-01

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Jonathan W. Oh ,  Fulvio Rori

IPC: G11C16/04 ,  G11C11/56

Abstract: Methods, systems, and devices for programming multi-level memory cells are described. After a first pass, an offset in the form of one or more offset pulses, may be applied to MLCs that are in a state of a higher level. The offset may be applied before or during a first part of a second pass. The offset may move the signals of the cells before the cells are finally programmed so as to avoid potential overlaps between the unprogrammed cells and cells that are programmed to the lower half of the final levels during the second pass. The offset cells may then be further moved to the other levels in the higher half of the final levels.

公开(公告)号：US11132247B2

公开(公告)日：2021-09-28

申请号：US16049439

申请日：2018-07-30

Applicant: Micron Technology, Inc.

Inventor： Fulvio Rori ,  Chiara Cerafogli ,  Scott Anthony Stoller

IPC: G06F11/07

Abstract: Aspects of the present disclosure include accessing block data stored in a memory component including memory blocks. The block data identifies bad blocks and reusable bad blocks, the reusable bad blocks having a higher level of reliability than bad blocks. Block selection is performed to select a block based on a block address. Based on the block selection and based on the block data, a tag operation is performed by setting a latch of the selected block to a first state in which access to the selected block is disabled.

公开(公告)号：US20210124511A1

公开(公告)日：2021-04-29

申请号：US17140600

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Chiara Cerafogli ,  Marco Domenico Tiburzi ,  Fulvio Rori

IPC: G06F3/06

Abstract: The disclosure describes a programmable power management system for NAND Flash devices. In one embodiment, dedicated match logic is provided to store program counters responsible for peak power consumption of one or more NAND Flash dies. Upon detecting that a current program counter equals a stored program counter, a high current enable signal is toggled causing at least one NAND Flash die to suspend operations, thereby reducing peak power consumption of the NAND Flash device.

公开(公告)号：US20200278907A1

公开(公告)日：2020-09-03

申请号：US16876788

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Fulvio Rori

IPC: G06F11/10 ,  G11C16/10 ,  G06F12/02 ,  G11C29/52 ,  G11C29/42

Abstract: Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.

公开(公告)号：US20200176067A1

公开(公告)日：2020-06-04

申请号：US16787199

申请日：2020-02-11

Applicant: Micron Technology, Inc.

Inventor： Fulvio Rori ,  Chiara Cerafogli

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/32 ,  G11C16/04

Abstract: An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

公开(公告)号：US20200034223A1

公开(公告)日：2020-01-30

申请号：US16049439

申请日：2018-07-30

Applicant: Micron Technology, Inc.

Inventor： Fulvio Rori ,  Chiara Cerafogli ,  Scott Anthony Stoller

IPC: G06F11/07

Abstract: Aspects of the present disclosure include accessing block data stored in a memory component including memory blocks. The block data identifies bad blocks and reusable bad blocks, the reusable bad blocks having a higher level of reliability than bad blocks. Block selection is performed to select a block based on a block address. Based on the block selection and based on the block data, a tag operation is performed by setting a latch of the selected block to a first state in which access to the selected block is disabled.

公开(公告)号：US20240427507A1

公开(公告)日：2024-12-26

申请号：US18827515

申请日：2024-09-06

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F3/06 ,  G06F1/08 ,  G06F1/28

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

公开(公告)号：US20240339158A1

公开(公告)日：2024-10-10

申请号：US18625800

申请日：2024-04-03

Applicant: Micron Technology, Inc.

Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Jeffrey S. McNeil ,  Tomoko Ogura Iwasaki ,  Yeang Meng Hern ,  Lee-eun Yu ,  Albert Fayrushin ,  Fulvio Rori ,  Justin Bates

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10

Abstract: Control logic in a memory device initiates a program operation including a first phase including applying a ramping voltage level to a set of wordlines of a memory device to boost a set of pillar voltages and a second phase including applying a set of programming pulses to a wordline associated with one or more memory cells of the memory device to be programmed to a set of programming levels, wherein each programming level of the set of programming levels is programmed by each programming pulse. During the first phase of the program operation, a first voltage applied to a drain-side select line (SGD) is adjusted from a first SGD voltage level to a second SGD voltage level.