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公开(公告)号：US12131028B2
公开(公告)日：2024-10-29
申请号：US18121494
申请日：2023-03-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jeffrey S. McNeil , Jonathan S. Parry , Ugo Russo , Akira Goda , Kishore Kumar Muchherla , Violante Moschiano , Niccolo' Righetti , Silvia Beltrami
CPC classification number: G06F3/0611 , G06F3/0659 , G06F3/0679
Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.
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32.发明公开公开(公告)号：US20240248616A1
公开(公告)日：2024-07-25
申请号：US18624657
申请日：2024-04-02
Applicant: Micron Technology, Inc.
Inventor： Sandeep Reddy Kadasani , Pitamber Shukla , Scott Anthony Stoller , Niccolo' Righetti
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/064 , G06F3/0653 , G06F3/0688
Abstract: A set of threshold voltage distribution width measurements are obtained for a block in a memory device. An endurance estimate is determined for the block based on the threshold voltage distribution width measurements. The endurance estimate comprises an indication of an estimated number of program/erase cycles during which data can be reliably stored by the block. One or more parameters of the block are managed based on the endurance estimate.
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公开(公告)号：US20240185926A1
公开(公告)日：2024-06-06
申请号：US18517903
申请日：2023-11-22
Applicant: Micron Technology, Inc.
Inventor： Huai-Yuan Tseng , Kishore Kumar Mucherla , William Charles Filipiak , Eric N. Lee , Andrew Bicksler , Ugo Russo , Niccolo' Righetti , Christian Caillat , Akira Goda , Ting Luo , Antonino Pollio
CPC classification number: G11C16/102 , G11C16/16 , G11C16/3404
Abstract: A variety of applications can include one or more memory devices having user data preloaded for the application prior to reflowing the memory devices on the system platform of the application. A touch-up data refresh method can be implemented to gain read window budget and to improve retention slope to protect the preload content to tolerate reflow to the system platform. Techniques for data preload can include programming preload data into targeted blocks until the targeted blocks are programmed with the preload data and re-programming the preload data over the programmed preload data in the targeted blocks in a same set of memory cells, without an erase between programming and re-programming the preload data. Variations of such techniques can be used to prepare a memory device with preload data followed by performing a reflow of the memory device to a structure for an application to which the memory device is implemented.
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公开(公告)号：US11922029B2
公开(公告)日：2024-03-05
申请号：US17863000
申请日：2022-07-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Jonathan S. Parry , Nicola Ciocchini , Animesh Roy Chowdhury , Akira Goda , Jung Sheng Hoei , Niccolo' Righetti , Ugo Russo
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0679
Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.
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公开(公告)号：US20230393756A1
公开(公告)日：2023-12-07
申请号：US17863000
申请日：2022-07-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Jonathan S. Parry , Nicola Ciocchini , Animesh Roy Chowdhury , Akira Goda , Jung Sheng Hoei , Niccolo' Righetti , Ugo Russo
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0679 , G06F3/0653
Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.
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Patent Agency Ranking
公开(公告)号：US11789629B2
公开(公告)日：2023-10-17
申请号：US17846462
申请日：2022-06-22
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil, Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
IPC: G06F3/06
CPC classification number: G06F3/0644 , G06F3/0616 , G06F3/0619 , G06F3/0653 , G06F3/0656 , G06F3/0673
Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.
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公开(公告)号：US11688479B2
公开(公告)日：2023-06-27
申请号：US17453289
申请日：2021-11-02
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Giuseppina Puzzilli , Karl D. Schuh , Jeffrey S. McNeil, Jr. , Kishore K. Muchherla , Ashutosh Malshe , Niccolo' Righetti
CPC classification number: G11C16/3495 , G11C16/14 , G11C16/26 , G11C16/32
Abstract: A first group of memory cells of a memory device can be subjected to a particular quantity of program/erase cycles (PECs) in response to a programming operation performed on a second group of memory cells of the memory device. Subsequent to subjecting the first group of memory cells to the particular quantity of PECs, a data retention capability of the first group of memory cells can be assessed.
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公开(公告)号：US11487436B2
公开(公告)日：2022-11-01
申请号：US16995083
申请日：2020-08-17
Applicant: Micron Technology, Inc.
Inventor： Jeffrey S. McNeil, Jr. , Niccolo' Righetti , Kishore K. Muchherla , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: Instructions can be executed to determine a quantity of logical units that are part of a memory device. The instructions can be executed to operate the logical units with a programming time sufficient to provide a required throughput for storage of time based telemetric sensor data received from a host. The instructions can be executed to operate the logical units with a trim that correspond to the programming time.
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公开(公告)号：US11437111B2
公开(公告)日：2022-09-06
申请号：US17122758
申请日：2020-12-15
Applicant: Micron Technology, Inc.
Inventor： Jeffrey S. McNeil, Jr. , Karl D. Schuh , Vamsi Pavan Rayaprolu , Giuseppina Puzzilli , Kishore K. Muchherla , Gil Golov , Todd A. Marquart , Jiangang Wu , Niccolo' Righetti , Ashutosh Malshe
Abstract: Instructions can be executed to adjust a trim at first intervals until a quantity of program/erase cycles (PEC) have occurred. The trim defines a valley width between data states. Instructions can be executed to adjust the trim at second intervals, greater than the first intervals, after the quantity of PEC have occurred.
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公开(公告)号：US11309052B2
公开(公告)日：2022-04-19
申请号：US17001723
申请日：2020-08-25
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil, Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.
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