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    Memory with partial bank refresh
    31.
    发明授权
    Memory with partial bank refresh 有权

    公开(公告)号：US11581031B2

    公开(公告)日：2023-02-14

    申请号：US17338191

    申请日：2021-06-03

    申请人： Micron Technology, Inc.

    发明人： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

    IPC分类号： G11C16/04 ,  G11C11/406 ,  G11C29/00 ,  G11C11/409 ,  G11C11/4074

    摘要： Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.

    Semiconductor device with user defined operations and associated methods and systems
    35.
    发明授权
    Semiconductor device with user defined operations and associated methods and systems 有权

    公开(公告)号：US11379299B2

    公开(公告)日：2022-07-05

    申请号：US17214684

    申请日：2021-03-26

    申请人： Micron Technology, Inc.

    发明人： Anthony D. Veches

    IPC分类号： G06F11/10

    摘要： Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.

    MEMORY WITH PARTIAL BANK REFRESH
    36.
    发明申请
    MEMORY WITH PARTIAL BANK REFRESH 有权

    公开(公告)号：US20210158863A1

    公开(公告)日：2021-05-27

    申请号：US16693949

    申请日：2019-11-25

    申请人： Micron Technology, Inc.

    发明人： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

    IPC分类号： G11C11/406 ,  G11C11/4074 ,  G11C11/409 ,  G11C29/00

    摘要： Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory row and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.

    Memory with on-die data transfer
    37.
    发明授权
    Memory with on-die data transfer 有权

    公开(公告)号：US10803926B2

    公开(公告)日：2020-10-13

    申请号：US16237115

    申请日：2018-12-31

    申请人： Micron Technology, Inc.

    发明人： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

    IPC分类号： G11C5/02 ,  G11C11/4093 ,  G11C11/406 ,  G11C7/18 ,  H01L25/10 ,  G11C11/4096

    摘要： Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.

    PHASE CHARGE SHARING REDUCTION
    38.
    发明申请
    PHASE CHARGE SHARING REDUCTION 审中-公开

    公开(公告)号：US20200185024A1

    公开(公告)日：2020-06-11

    申请号：US16216894

    申请日：2018-12-11

    申请人： Micron Technology, Inc.

    发明人： James S. Rehmeyer ,  George B. Raad ,  Debra M. Bell ,  Markus H. Geiger ,  Anthony D. Veches

    IPC分类号： G11C11/4094 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/408

    摘要： Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.

    Methods and systems for improving power delivery and signaling in stacked semiconductor devices
    40.
    发明授权
    Methods and systems for improving power delivery and signaling in stacked semiconductor devices 有权

    公开(公告)号：US10134712B1

    公开(公告)日：2018-11-20

    申请号：US15684703

    申请日：2017-08-23

    申请人： Micron Technology, Inc.

    发明人： Anthony D. Veches

    IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L23/64 ,  H01L25/00

    摘要： Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.