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    Integrated Assemblies and Methods of Forming Integrated Assemblies
    31.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 审中-公开

    公开(公告)号：US20190355711A1

    公开(公告)日：2019-11-21

    申请号：US16398433

    申请日：2019-04-30

    Applicant: Micron Technology, Inc.

    Inventor： Daniel Billingsley ,  Everett A. McTeer ,  Christopher W. Petz ,  Haoyu Li ,  John Mark Meldrim ,  Yongjun Jeff Hu

    IPC: H01L27/02 ,  G11C11/34 ,  H01L21/82 ,  H01L23/532 ,  H01L27/12 ,  G11C5/06

    Abstract: An integrated assembly includes an insulative mass with a first region adjacent to a second region. The first region has a greater amount of one or more inert interstitial elements incorporated therein than does the second region. Some embodiments include an integrated assembly which has vertically-extending channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure includes doped semiconductor material in direct contact with bottom regions of the channel material pillars. An insulative mass is along the bottom regions of the channel material pillars. The insulative mass has an upper region over a lower region. The lower region has a greater amount of one or more inert interstitial elements incorporated therein than does the upper region. Some embodiments include methods of forming integrated assemblies.

    Methods Used In Forming An Array Of Elevationally-Extending Transistors
    36.
    发明申请
    Methods Used In Forming An Array Of Elevationally-Extending Transistors 审中-公开

    公开(公告)号：US20190088671A1

    公开(公告)日：2019-03-21

    申请号：US15710432

    申请日：2017-09-20

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  E. Allen McTeer

    IPC: H01L27/11582 ,  H01L27/11556

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565

    Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (h) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.

    Methods of Forming Metal Silicide-Comprising Material and Methods of Forming Metal Silicide-Comprising Contacts
    37.
    发明申请
    Methods of Forming Metal Silicide-Comprising Material and Methods of Forming Metal Silicide-Comprising Contacts 有权
    形成金属硅化物的方法及其形成金属硅化物的方法

    公开(公告)号：US20140134816A1

    公开(公告)日：2014-05-15

    申请号：US14157192

    申请日：2014-01-16

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  John Mark Meldrim ,  Rita J. Klein

    IPC: H01L21/28 ,  H01L21/283

    CPC classification number: H01L21/28097 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32134 ,  H01L21/32139

    Abstract: A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.

    Abstract translation: 一种形成含金属硅化物的材料的方法包括形成衬底，该衬底包括具有超过硅的第一金属上的第二金属的第一堆叠和在硅上的第二金属的第二叠层。 第一和第二种金属具有不同的组成。 基板经受使第二金属与第二堆叠中的硅反应以形成来自第二堆叠的含金属硅化物的材料的条件。 第一堆叠中的第二金属和硅之间的第一金属阻止从第一堆叠形成包括第二金属和硅的硅化物。 在形成含金属硅化物的材料之后，对第一金属，第二金属和含金属硅化物的材料进行蚀刻化学，从而选择性地相对于金属硅化物从衬底中蚀刻至少一些剩余的第一和第二金属 令人惊奇的材料。

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