公开(公告)号：US06486025B1

公开(公告)日：2002-11-26

申请号：US10047265

申请日：2002-01-14

申请人： Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi ,  Chih-Hsing Yu

发明人： Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi ,  Chih-Hsing Yu

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L27/10811 ,  H01L28/84 ,  H01L28/91

摘要： Within a first of a pair of methods for forming a memory cell structure there is employed a sacrificial spacer layer formed adjacent a capacitor structure and subsequently stripped therefrom to provide an air gap void interposed between a bitline stud layer and the capacitor structure. Within a second of the pair of methods for forming a memory cell structure there is employed a topographically variable thickness masking layer as a self aligned mask layer for forming a patterned capacitor plate layer from a topographic blanket capacitor plate layer. The methods provide for readily forming the memory cell structure with enhanced performance.

摘要翻译： 在用于形成存储单元结构的一对方法中的第一种中，采用邻近电容器结构形成并随后从其中剥离的牺牲隔离层，以提供位于位线支柱层和电容器结构之间的气隙空隙。 在用于形成存储单元结构的一对方法的一秒钟内，采用形貌可变的厚度掩模层作为自对准掩模层，用于从地形覆盖电容器板层形成图案化电容器板层。 该方法提供了容易地形成具有增强性能的存储单元结构。

公开(公告)号：US06373090B1

公开(公告)日：2002-04-16

申请号：US09655026

申请日：2000-09-05

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/10814 ,  H01L27/10885 ,  H01L28/91

摘要： A structure with bit lines and capacitors for a semi-conductor memory device is formed by the following steps. Form a gate oxide layer on a doped silicon semiconductor substrate. Form gate electrode stacks juxtaposed with conductive plugs over the gate oxide layer, the conductive plugs being separated by a first dielectric material in a direction oriented transversely of the gate electrode stacks. Form a first interpolysilicon layer above the conductive plugs. Form bit-lines in the first interpolysilicon layer above the first dielectric material. Form a capacitor above a plug and between a pair of the bit-lines.

摘要翻译： 通过以下步骤形成具有用于半导体存储器件的位线和电容器的结构。 在掺杂硅半导体衬底上形成栅氧化层。 形成栅极电极堆叠在栅极氧化物层上方与导电插塞并置，导电插塞在横向于栅电极堆叠的方向上被第一介电材料隔开。 在导电插头上方形成第一个多晶硅层。 在第一介电材料上方的第一多晶硅内层中形成位线。 在插头之上和一对位线之间形成一个电容器。

公开(公告)号：US06362012B1

公开(公告)日：2002-03-26

申请号：US09798651

申请日：2001-03-05

申请人： Min-Hwa Chi ,  Chia-Shiung Tsai ,  Yeur-Luen Tu

发明人： Min-Hwa Chi ,  Chia-Shiung Tsai ,  Yeur-Luen Tu

IPC分类号： H01L2100

CPC分类号： H01L23/5223 ,  H01L23/5227 ,  H01L27/08 ,  H01L28/10 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method and structure is provided for the simultaneous creation of inductive and capacitive components in a monolithic substrate. The invention provides a method and structure whereby a vertical spiral inductor is created on the surface of a substrate. Multiple capacitors are created inside the coils of the vertical spiral conductor. A base layer of dielectric is deposited over the surface of a semiconductor substrate, contact plugs are provided in the base layer of dielectric. Multiple layers of dielectric are deposited over the surface of the base layer, layers of coils are created in the multiple layers of dielectric. Vias are provided in the layer of dielectric to interconnect overlying coils of the spiral inductor. An etch stop layer is deposited on the surface of the upper layer of dielectric. At least two openings are etched in the multiple layers of dielectric, these at least two openings are surrounded by the coils of the spiral inductor and align with the contact plugs provided in the base layers. Spacers are formed on the sidewalls of the openings, the bottom electrode layer, dielectric layer and top electrode layer of the at least two capacitors are deposited over the spacers. The openings are filled with a conductive material, the surface of the conductive material is polished down to the surface of the etch stop.

摘要翻译： 提供了一种新的方法和结构，用于在单片基板中同时产生感应和电容部件。 本发明提供一种方法和结构，由此在衬底的表面上产生垂直螺旋电感器。 在垂直螺旋导体的线圈内部产生多个电容器。 电介质的基底层沉积在半导体衬底的表面上，接触插塞设置在电介质的基底层中。 在基层的表面上沉积多层电介质，在多层电介质中形成线圈层。 在电介质层中提供通孔以互连螺旋电感器的上覆线圈。 蚀刻停止层沉积在电介质上层的表面上。 在多层电介质中蚀刻至少两个开口，这些至少两个开口被螺旋电感器的线圈包围，并与设置在基层中的接触插塞对准。 隔板形成在开口的侧壁上，至少两个电容器的底部电极层，电介质层和顶部电极层沉积在间隔物上。 开口填充有导电材料，导电材料的表面被抛光到蚀刻停止件的表面。

公开(公告)号：US06174767B1

公开(公告)日：2001-01-16

申请号：US09075370

申请日：1998-05-11

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10814 ,  H01L27/10885 ,  H01L28/91

摘要： A structure with bit lines and capacitors for a semiconductor memory device is formed by the following steps. Form a gate oxide layer on a doped silicon semiconductor substrate. Form gate electrode stacks juxtaposed with conductive plugs over the gate oxide layer, the conductive plugs being separated by a first dielectric material in a direction oriented transversely of the gate electrode stacks. Form a first interpolysilicon layer above the conductive plugs. Form bit-lines in the first interpolysilicon layer above the first dielectric material. Form a capacitor above a plug and between a pair of the bit-lines.

摘要翻译： 通过以下步骤形成具有用于半导体存储器件的位线和电容器的结构。 在掺杂硅半导体衬底上形成栅氧化层。 形成栅极电极堆叠在栅极氧化物层上方与导电插塞并置，导电插塞在横向于栅电极堆叠的方向上被第一介电材料隔开。 在导电插头上方形成第一个多晶硅层。 在第一介电材料上方的第一多晶硅内层中形成位线。 在插头之上和一对位线之间形成一个电容器。

公开(公告)号：US5936898A

公开(公告)日：1999-08-10

申请号：US53853

申请日：1998-04-02

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： G11C7/12 ,  G11C7/00

CPC分类号： G11C7/12

摘要： A voltage limiting isolation circuit for pairs of bit lines within a row of DRAM cells to reduce noise coupling will selectively connect and disconnect the portions of a primary and a complementary bit lines, onto which DRAM cells are attached, from the portions of the primary and the complementary bit lines, onto which latching sense amplifier and pre-charge and equalization circuit are attached. The voltage limiting bit line isolation circuit has two sets of serially connected N-type MOS transistors and first P-type MOS transistors placed on the primary bit line and the complementary bit line. Isolation voltage control circuits will provide voltages to the gates of the N-type MOS transistors and P-type MOS transistors to activate and deactivate the voltage limiting isolation control circuit. During a read cycle the latching sense amplifier will sense and amplify the charge from a selected cell and begin to force the first and second portions of the primary and complementary bit lines to a voltage level that is either that of the power supply voltage source or the ground. As the voltage level of the first and second portions of the primary and complementary bit lines approaches to within one threshold voltage level of the MOS transistors, the voltage limiting bit line isolation circuit will deactivate. The first portions of the primary and complementary bit lines will swing to a lower voltage level thus lowering coupled noise to adjacent bit lines.

摘要翻译： 用于一行DRAM单元内的一对位线的电压限制隔离电路以减少噪声耦合将选择性地将主单元和互补位线的部分连接到主单元和互补位线上 互补的位线，附加有锁存读出放大器和预充电和均衡电路。 电压限制位线隔离电路具有两组串联的N型MOS晶体管和放置在主位线和互补位线上的第一P型MOS晶体管。 隔离电压控制电路将向N型MOS晶体管和P型MOS晶体管的栅极提供电压，以激活和禁用限压隔离控制电路。 在读周期期间，锁存读出放大器将感测并放大来自所选单元的电荷，并开始将初级和互补位线的第一和第二部分强制为电源电压源或 地面。 当初级和互补位线的第一和第二部分的电压电平接近MOS晶体管的一个阈值电压电平时，电压限制位线隔离电路将停用。 初级和互补位线的第一部分将摆动到较低的电压电平，从而将耦合的噪声降低到相邻的位线。

公开(公告)号：US08435802B2

公开(公告)日：2013-05-07

申请号：US11438127

申请日：2006-05-22

申请人： Min-Hwa Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

发明人： Min-Hwa Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

IPC分类号： H01L21/00

CPC分类号： H01L21/76898 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.

摘要翻译： 通过退火工艺制备半导体器件，通过由绝缘体材料包围的导体线来互连器件的至少两个部件。 退火过程导致在导线和绝缘体材料内形成残余应力。 在掩模的选择性部分上的布局中设计凹口，用于图案化导体线。 选择部分上的凹口形状的存在在不存在凹口的情况下，在导线内产生额外的应力分量。 选择凹口的位置使得额外的应力分量基本上抵消残余应力，从而导致残余应力的净减小。 残余应力的减小导致相应的机械应力迁移，从而提高了装置的可靠性。

公开(公告)号：US08158512B2

公开(公告)日：2012-04-17

申请号：US12141040

申请日：2008-06-17

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno ,  Sean Fuxiong Zhang

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno ,  Sean Fuxiong Zhang

IPC分类号： H01L21/203

CPC分类号： C23C16/45529 ,  H01L21/28282 ,  H01L29/1608 ,  H01L29/42348 ,  H01L29/792

摘要： There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within a ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; forming a first dielectric layer to cover the discrete compound monolayer; forming a second third monolayer above first dielectric layer; and forming a second discrete compound monolayer; and forming a second dielectric layer to cover the second discrete compound monolayer above the first dielectric layer. There is also provided a semiconductor device formed by the ALD method.

摘要翻译： 提供一种制造半导体器件的方法，包括以下步骤：在ALD室内使第一前体气体流到半导体衬底，以在半导体衬底上形成第一离散单层; 将惰性吹扫气体流入ALD室内的半导体衬底; 使第二前体气体流到ALD室以与形成第一单层的第一前体气体反应，从而形成第一离散化合物单层; 并流动惰性吹扫气体; 形成第一电介质层以覆盖离散化合物单层; 在第一介电层上形成第二第三单层; 并形成第二离散化合物单层; 以及形成第二电介质层以覆盖所述第一电介质层上方的所述第二离散化合物单层。 还提供了通过ALD方法形成的半导体器件。

公开(公告)号：US07994040B2

公开(公告)日：2011-08-09

申请号：US11785023

申请日：2007-04-13

申请人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang ,  Chang-Ku Chen

发明人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang ,  Chang-Ku Chen

IPC分类号： H01L21/4763

CPC分类号： H01L29/665 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y02P80/30

摘要： A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer. The opening is sealed by a sealing layer to form an air gap.

摘要翻译： 公开了一种用于形成半导体器件的方法。 提供了包括顺序地形成在其上的栅介电层和栅极电极层的基板。 在栅极电介质层和栅极电极层的侧壁上形成偏移间隔物。 在间隔物的侧壁上形成碳隔离物，然后除去碳隔离物。 使用栅极电极层和偏移间隔物作为掩模，注入衬底以形成轻掺杂区域。 该方法还可以包括提供具有顺序地形成在其上的栅极电介质层和栅极电极层的衬底。 衬底层形成在栅电极层的侧壁和衬底上。 在衬垫层的与栅电极层的侧壁相邻的部分上形成碳隔离物。 主间隔件形成在碳隔离件的侧壁上。 去除碳间隔物以在衬垫层和主间隔物之间​​形成开口。 开口由密封层密封以形成气隙。

公开(公告)号：US07498657B2

公开(公告)日：2009-03-03

申请号：US11102340

申请日：2005-04-08

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： H01L29/00

CPC分类号： H01L27/0802 ,  H01L29/7722 ,  H01L29/8083 ,  H01L29/8605

摘要： A vertical resistor. A substrate includes a trench filled by an isolation layer. A first doped-type region and a second doped-type region are formed on both sides of the trench. The first doped-type region receives a control bias, the second doped-type region receives a reference bias, and a resistance between the second doped-type region and the substrate is adjusted in response to a voltage difference between the control bias and the reference bias.

摘要翻译： 一个垂直电阻。 衬底包括由隔离层填充的沟槽。 第一掺杂型区域和第二掺杂型区域形成在沟槽的两侧。 第一掺杂型区域接收控制偏压，第二掺杂型区域接收参考偏置，并且响应于控制偏压和参考电压之间的电压差来调整第二掺杂型区域和衬底之间的电阻 偏压。

公开(公告)号：US20080315293A1

公开(公告)日：2008-12-25

申请号：US12141045

申请日：2008-06-17

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

IPC分类号： H01L21/28 ,  H01L29/792

CPC分类号： H01L21/0228 ,  C23C16/45529 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/31645 ,  H01L21/318 ,  H01L21/3185 ,  H01L27/11563

摘要： There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method.

摘要翻译： 提供一种制造半导体器件的方法，包括以下步骤：将第一前体气体流到ALD室内的半导体衬底，以在半导体衬底上形成第一离散单层; 将惰性吹扫气体流入ALD室内的半导体衬底; 使第二前体气体流到ALD室以与形成第一单层的第一前体气体反应，从而形成第一离散化合物单层; 并流动惰性吹扫气体; 以及通过与形成第一离散化合物单层相同的方法在半导体衬底上方形成第二离散化合物单层。 还提供了一种半导体器件，其中电荷捕获层是包含通过ALD法形成的第一和第二离散化合物单层的电介质层。