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    Techniques for testing semiconductor devices
    31.
    发明授权
    Techniques for testing semiconductor devices 有权

    公开(公告)号：US12079097B2

    公开(公告)日：2024-09-03

    申请号：US17075628

    申请日：2020-10-20

    Applicant: NVIDIA CORPORATION

    Inventor： Animesh Khare ,  Ashish Kumar ,  Shantanu Sarangi ,  Rahul Garg

    IPC: G06F11/273 ,  G06F11/22 ,  G06F13/28 ,  G06F13/42

    CPC classification number: G06F11/2733 ,  G06F11/2268 ,  G06F13/28 ,  G06F13/4282 ,  G06F2213/0026

    Abstract: Techniques for testing semiconductor devices include a semiconductor device having a plurality of components, a test bus, and a test data transfer unit. The test data transfer unit receives, from a host computer, configuration information for performing a test of the semiconductor device, reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, sends the test data to the plurality of components via the test bus, causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test, and after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.

    Controlling test networks of chips using integrated processors
    34.
    发明授权
    Controlling test networks of chips using integrated processors 有权

    公开(公告)号：US11526644B2

    公开(公告)日：2022-12-13

    申请号：US17089864

    申请日：2020-11-05

    Applicant: Nvidia Corporation

    Inventor： Kaushik Narayanun ,  Mahmut Yilmaz ,  Shantanu Sarangi ,  Jae Wu

    IPC: G06F30/333 ,  G01R31/317 ,  G01R31/3185 ,  G06F30/394 ,  G06F30/323 ,  G06F115/12 ,  G06F115/02

    Abstract: The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.

    Leveraging low power states for fault testing of processing cores at runtime
    35.
    发明授权
    Leveraging low power states for fault testing of processing cores at runtime 有权

    公开(公告)号：US11204849B2

    公开(公告)日：2021-12-21

    申请号：US16818327

    申请日：2020-03-13

    Applicant: NVIDIA Corporation

    Inventor： Jonah Alben ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

    IPC: G06F11/267 ,  G06F11/22 ,  G06F11/273 ,  G06F11/27 ,  G06F1/3296

    Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

    Granular dynamic test systems and methods
    36.
    发明授权
    Granular dynamic test systems and methods 有权

    公开(公告)号：US10481203B2

    公开(公告)日：2019-11-19

    申请号：US15478176

    申请日：2017-04-03

    Applicant: NVIDIA Corporation

    Inventor： Shantanu Sarangi ,  Milind Sonawane ,  Adarsh Kalliat Balagopala ,  Amit Sanghani

    IPC: G01R31/317 ,  G01R31/3185 ,  G06F11/00

    Abstract: In one embodiment, a system comprises: a global clock input for receiving a global clock, a plurality of partitions; and a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the partitions and a balanced local clock within at least one of the partitions. The partitions can be test partitions. The skew tolerant interface can cross a mesochronous boundary. In one exemplary implementation, the skew tolerant interface includes a deskew ring buffer on communication path of the at least one partition. pointers associated with the ring buffer can be free-running and depend only on clocks being pulsed when out of reset. The scheme can be fully synchronous and deterministic. The scheme can be modeled for the ATPG tools using simple pipeline flops. The depth of the pipeline can be dependent on the pointer difference for the read/write interface. The global clock input can be part of a scan link.

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