公开(公告)号：US06188626B1

公开(公告)日：2001-02-13

申请号：US09268920

申请日：1999-03-16

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A method of refreshing DRAM. The method of the invention utilizes the time, in which CPU is executing a cache hit cycle, an input/output cycle, an interrupt acknowledge cycle or an idle cycle, to perform a least one refresh cycle for refreshing DRAM. It uses the time, in which CPU does not access DRAM, to perform the refresh cycle. Besides, it needs to insert the rest of the refresh cycles, which are required to be accomplished during a fixed time period, to replace any operational cycle of DRAM before the end of the fixed time period comes.

摘要翻译： 一种刷新DRAM的方法。 本发明的方法利用CPU执行高速缓存命中循环，输入/输出周期，中断确认周期或空闲周期的时间来执行用于刷新DRAM的至少一个刷新周期。 它使用CPU不访问DRAM的时间来执行刷新周期。 此外，在固定时间段结束之前，需要插入在固定时间段内完成的其余刷新周期以替代DRAM的任何操作周期。

公开(公告)号：US6134701A

公开(公告)日：2000-10-17

申请号：US159441

申请日：1998-09-22

申请人： Shu-Hui Chen ,  Tsai-Sheng Chen ,  Nai-Shung Chang

发明人： Shu-Hui Chen ,  Tsai-Sheng Chen ,  Nai-Shung Chang

IPC分类号： G06F12/08 ,  H05K1/18 ,  G06F3/00

CPC分类号： H05K1/181 ,  G06F12/0893 ,  H05K2201/09227 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611

摘要： The present invention provides a computer motherboard having an Intel P54C compatible processor socket and a control chip having specifically arranged data pins and address pins which allows a short signal path arrangement from the processor socket to a cache tap RAM and a cache data RAM. The computer motherboard comprises a four-layer printed circuit board, a processor socket, a cache data RAM, a cache tag RAM, and a control chip. All these components are connected by using a high-order-bit data bus, a low-order-bit data bus, and an address bus through the top and bottom layers of the circuit board. The cache data RAM is positioned on the right side of the processor socket. The control chip is positioned on the top side of the cache data RAM and on the top-right side of the processor socket. It comprises an address section positioned at a bottom-middle portion of the control chip, a high-order-bit data section positioned at a bottom-right corner of the control chip, and a low-order-bit data section positioned at a bottom-left corner of the control chip. The cache tag RAM is positioned between the processor socket and the cache data RAM.

摘要翻译： 本发明提供了一种具有Intel P54C兼容处理器插座的计算机主板和具有特别布置的数据引脚和地址引脚的控制芯片，其允许从处理器插槽到高速缓存分接器RAM和高速缓存数据RAM的短信号路径布置。 计算机主板包括四层印刷电路板，处理器插座，高速缓存数据RAM，高速缓存标签RAM和控制芯片。 所有这些组件通过使用高位数据总线，低位数据总线和通过电路板的顶层和底层的地址总线连接。 缓存数据RAM位于处理器插槽的右侧。 控制芯片位于高速缓存数据RAM的顶侧，并位于处理器插槽的右上侧。 它包括位于控制芯片的底部中间部分的地址部分，位于控制芯片的右下角的高位数据部分和位于底部的低位数据部分 - 控制芯片的左角。 高速缓存标签RAM位于处理器插槽和高速缓存数据RAM之间。

公开(公告)号：US6072334A

公开(公告)日：2000-06-06

申请号：US206051

申请日：1998-12-04

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： H03K19/0175

CPC分类号： H03K19/017581

摘要： A signal converter with a dynamically adjustable reference voltage according to the invention, which can receive different qualities of signals. The signal converter includes an input circuit and a reference voltage generator. The input circuit converts a first digital signal, such as a GTL+ signal, into a second digital signal, such as a TTL or CMOS signal, based on an adjustable reference voltage generated by the reference voltage generator. When a control circuit needs to receive the first digital signal from outside via the input circuit, the control circuit can adjust the reference voltage by controlling the reference voltage generator so as to receive the first digital signal with a different quality.

摘要翻译： 具有根据本发明的动态可调参考电压的信号转换器，其可以接收不同质量的信号。 信号转换器包括输入电路和参考电压发生器。 输入电路基于由参考电压发生器产生的可调参考电压将诸如GTL +信号的第一数字信号转换成第二数字信号，例如TTL或CMOS信号。 当控制电路需要经由输入电路从外部接收第一数字信号时，控制电路可以通过控制参考电压发生器来调节参考电压，以便以不同的质量接收第一数字信号。

公开(公告)号：US06034508A

公开(公告)日：2000-03-07

申请号：US200331

申请日：1998-11-25

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： H02J9/06 ,  H01M10/42 ,  H01M10/48 ,  H02J7/00

CPC分类号： H02J7/0068 ,  Y10T307/505

摘要： A power-source-switching device automatically capable of directing power from a battery or an external power source to an all-time circuit. When the external power source is connected, a switching circuit directs the external power source to the all-time circuit. On the other hand, when the external power source is disconnected, the switching circuit is able to direct power from the battery to the all-time circuit. Since the conventional diode connection is replaced by a switching circuit, a voltage drop across the diode due to forward bias is avoided. Consequently, the battery can work at a lower voltage level, thereby extending the working life of a battery.

摘要翻译： 电源切换装置能够自动地将来自电池或外部电源的电力引导到全时电路。 当外部电源连接时，开关电路将外部电源引导到全时电路。 另一方面，当外部电源断开时，开关电路能够将电力从电池引导到全时电路。 由于传统的二极管连接被开关电路代替，所以避免了由于正向偏压引起的二极管两端的电压降。 因此，电池可以在较低的电压水平工作，从而延长电池的使用寿命。

公开(公告)号：US20070013045A1

公开(公告)日：2007-01-18

申请号：US11257593

申请日：2005-10-24

申请人： Chih-Hsiung Lin ,  Nai-Shung Chang

发明人： Chih-Hsiung Lin ,  Nai-Shung Chang

IPC分类号： H01L23/48 ,  H01L23/28

CPC分类号： H05K1/0209 ,  H01L23/367 ,  H01L23/3735 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10734

摘要： A printed circuit board (PCB) for a package substrate of a multi-package module (MPM). The PCB comprises a substrate and a heat sink thereon. The heat sink comprises a first portion under the package substrate of the MPM. The heat sink further comprises a second portion adjacent to the first portion, comprising at least one fin.

公开(公告)号：US07030502B2

公开(公告)日：2006-04-18

申请号：US10249179

申请日：2003-03-20

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： H01L23/48

CPC分类号： H01L23/13 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wire bonding BGA package. On a conductive metal layer of a substrate used for carrying a die, a power ring for providing an operating voltage to a core circuit of the die is disposed in the inner side of a power ring for providing an operating voltage to an input/output circuit of the die. When the die is packaged by flip chip packaging instead of wire bonding packaging, the power ballout assignment of the BGA package is unchanged and is suitable for matching with an original circuit board used for the flip chip BGA package. In addition, the present invention provides a flip chip BGA package. When the die is packaged by wire bonding packaging instead of flip chip packaging, the power ballout assignment of the BGA package is unchanged and is suitable for matching with an original circuit board used for the wire bonding BGA package.

摘要翻译： 引线键合BGA封装。 在用于承载芯片的基板的导电金属层上，用于向芯片的芯电路提供工作电压的电源环设置在电源环的内侧，用于向输入/输出电路提供工作电压 的死亡。 当晶片通过倒装芯片封装而不是引线键合封装封装时，BGA封装的功率调整分配不变，适合与用于倒装芯片BGA封装的原始电路板匹配。 此外，本发明提供一种倒装芯片BGA封装。 当裸片通过引线接合封装而不是倒装芯片封装封装时，BGA封装的功率调配不变，适合与用于引线接合BGA封装的原始电路板匹配。

公开(公告)号：US06870250B2

公开(公告)日：2005-03-22

申请号：US10217347

申请日：2002-08-08

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： H01L23/498 ,  H01L23/64 ,  H01L23/48

CPC分类号： H01L23/49838 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip package structure having a substrate therein for accommodating a die. Power regions supplying power to various control units within the die are grouped together into at least two sections. At least one π filter is used to isolate different power regions on the substrate so that cross interference of noise signals are reduced and stability of the chip is improved. The π filter is positioned close to one of the corners of the substrate so that the layout of wiring on the substrate is facilitated.

摘要翻译： 一种芯片封装结构，其中具有用于容纳管芯的衬底。 向芯片内的各种控制单元供电的功率区域分组为至少两个部分。 使用至少一个π滤波器来隔离衬底上的不同功率区域，从而降低噪声信号的交叉干扰并提高芯片的稳定性。 pi滤光器靠近基板的一个角部，从而便于基板上布线的布局。

公开(公告)号：US20050027895A1

公开(公告)日：2005-02-03

申请号：US10930117

申请日：2004-08-30

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F13/40 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0175

CPC分类号： G06F13/4072

摘要： An I/O pad has a data transmitting circuit, a data monitoring control circuit, and a control selection circuit. The control selection circuit controls the data transmitting circuit at the control end, so as to enable or disable the transmission. When it is enabled, data in the data transmitting circuit are exported to a receiving circuit. When it is disabled, data exportation stops. The data monitoring circuit receives signals of the data transmission circuit and export signals to the control selection circuit. The data monitoring circuit judges whether the data transmission is under a stable condition. If it is not yet, an unstable signal is exported to a first input end of the control selection circuit. A second input end of the control selection circuit receives an output enabling signal. The output end of the control selection circuit is connected to the control end of the data transmitting circuit. When the data transmission is at stable status and the output enabling signal indicates a disable status, the control selection circuit disables the data transmitting circuit. Otherwise, the control selection circuit enables the data transmitting circuit.

摘要翻译： I / O焊盘具有数据发送电路，数据监视控制电路和控制选择电路。 控制选择电路控制控制端的数据发送电路，以使能或禁止发送。 当使能时，数据发送电路中的数据被输出到接收电路。 禁用数据后，数据导出停止。 数据监视电路接收数据传输电路的信号并将信号输出到控制选择电路。 数据监视电路判断数据传输是否处于稳定状态。 如果还没有，则将不稳定的信号输出到控制选择电路的第一输入端。 控制选择电路的第二输入端接收输出使能信号。 控制选择电路的输出端连接到数据发送电路的控制端。 当数据传输处于稳定状态并且输出使能信号指示禁止状态时，控制选择电路禁止数据发送电路。 否则，控制选择电路使能数据发送电路。

公开(公告)号：US06794744B2

公开(公告)日：2004-09-21

申请号：US10064426

申请日：2002-07-12

申请人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC分类号： H01L2352

CPC分类号： H05K1/0295 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09345 ,  H05K2201/09954 ,  H05K2201/10522 ,  H05K2201/10704 ,  H05K2201/10734

摘要： A layout structure of a central processing unit (CPU) that supports two different package techniques, having a motherboard that comprising the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially placed a top signal layer, a grounded layer, a power layer having an operating potential area and a grounded potential area, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer.

摘要翻译： 中央处理单元（CPU）的布局结构，其支持两种不同的封装技术，具有包括布局结构的主板和布局方法。 根据本发明的优选实施例的布局结构从上到下顺序地放置了顶部信号层，接地层，具有工作电位区域的功率层和接地电位区域，以及底部焊料层， CPU的信号耦合到控制芯片的信号，使得放置在底部焊料层上的信号可以指功率层的接地电位区域。

公开(公告)号：US06667634B2

公开(公告)日：2003-12-23

申请号：US10138021

申请日：2002-05-03

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F738

CPC分类号： G06F13/4072

摘要： A multi-option setting device is provided for use in association with a connecting pin of a chipset for allowing user-selection from more than two setting options to set the chipset to perform one of more than two I/O functions through the associated connecting pin. The multi-option setting device includes voltage setting means for generating a user-specified input voltage; voltage comparison circuits for use to determine which pre-specified voltage range the user-specified input voltage lies; and latch circuits each for latching the corresponding output of the voltage comparison circuits. This allows the associated connecting pin to be optionally set to be used for a user-specified I/O function.