Abstract:
A hybrid-bonded image sensor has a photodiode die with multiple macrocells; each macrocell has at least one photodiode and a coupling region. The coupling regions couple to a coupling region of a macrocell unit of a supporting circuitry die where they feed an input of an amplifier and a feedback capacitor. The feedback capacitor also couples to output of the amplifier, and the amplifier inverts between the input and the output. The method includes resetting a photodiode of the photodiode die; coupling signal from photodiode through the bond point to the supporting circuitry die to a feedback capacitor and to an input of the amplifier, the feedback capacitor also coupled to an inverting output of the amplifier; and amplifying the signal with the amplifier, where a capacitance of the feedback capacitor determines a gain of the amplifier.
Abstract:
A shared pixel includes a plurality of transfer gates coupled between respective photodiodes and a shared floating diffusion. Each transfer gate is coupled to receive a transfer control signal to independently control a transfer of the image charge from the corresponding photodiodes to the shared floating diffusion. Each transfer control signal is set to one of an ON value, a first OFF value, and a second OFF value. One of the control signals that is coupled to an active transfer gate is set to the ON value during a transfer operation. The control signals coupled to idle transfer gates are set to the first OFF value during a reset period prior to the transfer operation, and are set to the second OFF value during the transfer operation.
Abstract:
A pixel circuit includes a photodiode, and a transfer transistor coupled to the photodiode. A floating diffusion is coupled to the transfer transistor coupled to transfer image charge from the photodiode to the floating diffusion. An amplifier circuit includes an input coupled to the floating diffusion, an output coupled to generate an image data signal of the pixel circuit, and a variable bias terminal coupled to receive a variable bias signal. A reset switch is coupled between the output and input of the amplifier circuit to reset the amplifier circuit in response to a reset signal. A variable bias generator circuit is coupled to generate the variable bias signal in response to a reset signal to transition the variable bias signal from a first bias signal value to a second bias signal value in response to a transition of the reset signal from an active state to an inactive state.
Abstract:
A method of focusing an image sensor includes scanning a first portion of an image frame from an image sensor a first time at a first rate to produce first focus data. A second portion of the image frame from the image sensor is scanned at a second rate to read image data from the second portion. The first rate is greater than the second rate. The first portion of the image frame is scanned a second time at the first rate to produce second focus data. The first focus data and the second focus data are compared, and the focus of a lens is adjusted in response to the comparison of the first focus data and the second focus data.
Abstract:
An example ramp analog-to-digital converter (ADC) for generating at least one bit of a digital signal includes a modified ramp signal generator, a comparator, and a control circuit. The modified ramp signal generator receives a ramp signal and generates a modified ramp signal in response thereto. The comparator compares an analog input with the modified ramp signal. The control circuit controls the modified ramp signal generator, such that the analog input is converted a variable M number of times for each period of the ramp signal. The number M is dependent on a magnitude of the analog input. In one example, the number M is greater for analog inputs of a lower magnitude, such that the analog inputs of the lower magnitude are converted more times than analog inputs of a higher magnitude.
Abstract:
A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.
Abstract:
A subrange analog-to-digital converter (ADC) converts analog image signal received from a bitline to a digital signal through an ADC comparator. The comparator is shared by a successive approximation register (SAR) ADC coupled to provide M upper output bits (UOB) of the subrange ADC and a ramp ADC coupled to provide N lower output bits (LOB). The digital-to-analog converter (DAC) of the SAR ADC comprises M buffered bit capacitors connected to the comparator. Each buffered bit capacitor comprises a bit capacitor, a bit buffer, and a bit switch controlled by one of the UOB of the SAR ADC. A ramp buffer is coupled between a ramp generator and a ramp capacitor. The ramp capacitor is further coupled to the same comparator. The implementation of ramp buffer and the bit buffers as well as their sharing of the same kind of buffer reduces differential nonlinear (DNL) error of the subrange ADC.
Abstract:
An image sensor includes a pixel array including a plurality of pixels. Each pixel is coupled to generate image data in response to incident light. A bit line is coupled to a column of pixels of the pixel array and is separated into first and second portions. Each portion is coupled to a corresponding portion of rows of pixels of the pixel array. A readout circuit coupled to the bit line to read out the image data from the pixel array. The readout circuit includes a cascode device coupled between the first and second portions of the bit line. The cascode device is coupled to be biased to electrically separate the first and second portions of the bit line from one another such that a capacitance of each portion of the bit line does not affect a settling time of an other portion of the bit line.
Abstract:
An active depth imaging system and method of operating the same captures illuminator-on and illuminator-off image data with each of a first and second imager. The illuminator-on image data includes information representing an imaged scene and light emitted from an illuminator and reflected off of objects within the imaged scene. The illuminator-off image data includes information representing the imaged scene without the light emitted from the illuminator. For each image set captured by the first and second imagers, illuminator-off image data is subtracted from the illuminator-on image data to identify the illuminated light within the scene. The depth of an object at which the light is incident on then is determined by the subtracted image data of the first and second imagers.
Abstract:
A group of shared pixels comprises: a first shared pixel comprising a first photodiode and a first transfer gate; a second shared pixel comprising a second photodiode and a second transfer gate; a third shared pixel comprising a third photodiode and a third transfer gate; a fourth shared pixel comprising a fourth photodiode and a first transfer gate; a first floating diffusion shared by the first shared pixel and the second shared pixel; a second floating diffusion shared by the third shared pixel and the fourth shared pixel; a capacitor coupled to the first floating diffusion through a first dual conversion gain transistor, and the second floating diffusion through a second dual conversion gain transistor; wherein the capacitor is formed in an area covering most of the first shared pixel, the second shared pixel, the third shared pixel, and the fourth shared pixel.