公开(公告)号：US07531388B2

公开(公告)日：2009-05-12

申请号：US11876942

申请日：2007-10-23

申请人： Roger A. Booth, Jr. ,  William R. Tonti ,  Jack A. Mandelman

发明人： Roger A. Booth, Jr. ,  William R. Tonti ,  Jack A. Mandelman

IPC分类号： H01L21/82 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.

摘要翻译： 提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。 第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。 狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。 变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。 在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

公开(公告)号：US07417300B2

公开(公告)日：2008-08-26

申请号：US11372386

申请日：2006-03-09

申请人： Roger A. Booth, Jr. ,  Jack A. Mandelman ,  William R. Tonti

发明人： Roger A. Booth, Jr. ,  Jack A. Mandelman ,  William R. Tonti

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.

摘要翻译： 提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。 第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。 狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。 变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。 在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

公开(公告)号：US08846470B2

公开(公告)日：2014-09-30

申请号：US13153538

申请日：2011-06-06

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/8242 ,  H01L49/02 ,  H01L21/762 ,  H01L29/66 ,  H01L21/74 ,  H01L27/06

CPC分类号： H01L27/10829 ,  H01L21/743 ,  H01L21/76283 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/60 ,  H01L28/92 ,  H01L29/0649 ,  H01L29/66181

摘要： A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

摘要翻译： 提供了高k电介质金属沟槽电容器和改进的隔离及其制造方法。 该方法包括在衬底中形成至少一个深沟槽，并用牺牲填充材料和聚合材料填充深沟槽。 该方法还包括继续CMOS工艺，包括形成至少一个晶体管和后端（BEOL）层。 该方法还包括从深沟槽去除牺牲填充材料以暴露侧壁，以及在深沟槽的暴露的侧壁上形成电容器板。 该方法还包括用高k电介质材料衬套电容器板，并用金属材料在高k电介质材料上填充深沟槽的剩余部分。 该方法还包括在填充有金属材料和高k电介质材料的深沟槽上提供钝化层。

公开(公告)号：US08829585B2

公开(公告)日：2014-09-09

申请号：US13118881

申请日：2011-05-31

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  David M. Fried ,  Byeong Y. Kim ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  David M. Fried ,  Byeong Y. Kim ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L29/92 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1203

摘要： In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.

摘要翻译： 在垂直动态存储单元中，通过在绝缘体材料上的横向外延生长（其补充电容器电介质完全围绕存储节点，除了接触连接结构，优选地，存储晶体管的沟道）为存取晶体管的沟道提供改善的质量的单晶半导体材料 的金属，从存取晶体管到存储节点电极），并蚀刻掉包括最可能发生晶格位错的位置的横向外延生长的区域; 这两个特征用于减少或避免从存储节点泄漏电荷。 可以在蚀刻区域中提供隔离结构，使得提供用于连接到存储单元阵列的各个部分的空间。

公开(公告)号：US08647945B2

公开(公告)日：2014-02-11

申请号：US12959824

申请日：2010-12-03

申请人： Geng Wang ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

发明人： Geng Wang ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC分类号： H01L21/70

CPC分类号： H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

摘要： A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

摘要翻译： 提供一种半导体结构，其包括在基底半导体层上包含外延生长的半导体层的材料堆叠，外延生长的半导体层上的电介质层和存在于电介质层上的上半导体层。 存在从上半导体层通过电介质层延伸到与外延生长的半导体层接触的电容器。 电容器包括存在于沟槽的侧壁上的节点电介质和填充沟槽的至少一部分的上电极。 在从上半导体层通过电介质层和外延半导体层延伸到基底半导体层的掺杂区域的接触沟槽中存在衬底接触。 还提供了通过沟槽的侧壁接触基底半导体层的衬底接触。 还提供了形成上述结构的方法。

公开(公告)号：US08629009B2

公开(公告)日：2014-01-14

申请号：US13433423

申请日：2012-03-29

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/28282 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

摘要： A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

摘要翻译： 提供一种制造存储器件的方法，其可以开始于在半导体衬底顶上形成分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和 半导体衬底上的第二金属栅电极。 在下一个处理顺序中，在第一金属栅电极的高k栅介质层的一部分顶上形成至少一个间隔物，其中高k栅极电介质的剩余部分被暴露。 蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质 到第二金属栅电极的侧壁。

公开(公告)号：US08513723B2

公开(公告)日：2013-08-20

申请号：US12689743

申请日：2010-01-19

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L28/40

摘要： An integrated circuit is provided that includes a fully depleted semiconductor device and a capacitor present on a semiconductor on insulator (SOI) substrate. The fully depleted semiconductor device may be a finFET semiconductor device or a planar semiconductor device. In one embodiment, the integrated circuit includes a substrate having a first device region and a second device region. The first device region of the substrate includes a first semiconductor layer that is present on a buried insulating layer. The buried insulating layer that is in the first device region is present on a second semiconductor layer of the substrate. The second device region includes the second semiconductor layer, but the first semiconductor layer and the buried insulating layer are not present in the second device region. The first device region includes the fully depleted semiconductor device. A capacitor is present in the second device region.

摘要翻译： 提供了一种集成电路，其包括完全耗尽的半导体器件和存在于半导体绝缘体（SOI））衬底上的电容器。 完全耗尽的半导体器件可以是finFET半导体器件或平面半导体器件。 在一个实施例中，集成电路包括具有第一器件区域和第二器件区域的衬底。 衬底的第一器件区域包括存在于掩埋绝缘层上的第一半导体层。 在第一器件区域中的掩埋绝缘层存在于衬底的第二半导体层上。 第二器件区域包括第二半导体层，但是第二器件区域中不存在第一半导体层和掩埋绝缘层。 第一器件区域包括完全耗尽的半导体器件。 电容器存在于第二器件区域中。

公开(公告)号：US08455768B2

公开(公告)日：2013-06-04

申请号：US12946294

申请日：2010-11-15

申请人： Roger A. Booth, Jr. ,  Lawrence A. Clevenger

发明人： Roger A. Booth, Jr. ,  Lawrence A. Clevenger

IPC分类号： H05K1/09 ,  H01C1/02

CPC分类号： H01L28/20 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76831 ,  H01L23/5228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T29/49082 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

摘要： A stack of an interconnect-level dielectric material layer and a disposable dielectric material layer is patterned so that at least one recessed region is formed through the disposable dielectric material layer and in an upper portion of the interconnect-level dielectric material layer. A dielectric liner layer and a metallic liner layer is formed in the at least one recessed region. At least one photoresist is applied to fill the at least one recessed region and lithographically patterned to form via cavities and/or line cavities in the interconnect-level dielectric material layer. After removing the at least one photoresist, the at least one recessed region, the via cavities, and/or the line cavities are filled with at least one metallic material, which is subsequently planarized to form at least one planar resistor having a top surface that is coplanar with top surfaces of metal lines or metal vias.

摘要翻译： 互连级介电材料层和一次性介电材料层的堆叠被图案化，使得通过一次性介电材料层和互连级介电材料层的上部形成至少一个凹陷区域。 在所述至少一个凹部区域中形成介电衬垫层和金属衬垫层。 施加至少一个光致抗蚀剂以填充至少一个凹陷区域并且被光刻图案化以在互连级介电材料层中形成通孔和/或线腔。 在去除至少一个光致抗蚀剂之后，至少一个凹陷区域，通孔腔体和/或线腔体填充有至少一种金属材料，其随后被平坦化以形成至少一个具有顶表面的平面电阻器， 与金属线或金属通孔的顶面共面。

公开(公告)号：US08378450B2

公开(公告)日：2013-02-19

申请号：US12548484

申请日：2009-08-27

申请人： Roger A. Booth, Jr. ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He

发明人： Roger A. Booth, Jr. ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/90 ,  H01L23/5223 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

摘要翻译： 叉指结构可以包括至少一个第一金属线，平行于至少一个第一金属线并与至少一个第一金属线分离的至少一个第二金属线，以及接触至少一个第一金属线的端部的第三金属线 第一金属线并且与所述至少一个第二金属线分离。 所述至少一个第一金属线不垂直接触任何金属通孔，并且至少一个第二金属线可垂直接触至少一个金属通孔。 多层交错结构可以垂直堆叠。 替代地，叉指结构可以包括多个第一金属线和多个第二金属线，每个金属线不垂直地接触任何金属通孔。 交错结构的多个实例可以横向复制和邻接，具有或不具有旋转和/或垂直堆叠以形成电容器。

公开(公告)号：US08222104B2

公开(公告)日：2012-07-17

申请号：US12509780

申请日：2009-07-27

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/8242

CPC分类号： H01L29/945 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/0805 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit device includes forming a plurality of deep trench decoupling capacitors on a first substrate; forming a plurality of active circuit devices on a second substrate; bonding the second substrate to the first substrate; and forming electrical connections between the deep trench capacitors and the second substrate.

摘要翻译： 形成集成电路器件的方法包括在第一衬底上形成多个深沟槽去耦电容器; 在第二基板上形成多个有源电路器件; 将所述第二基板接合到所述第一基板; 以及在所述深沟槽电容器和所述第二衬底之间形成电连接。