公开(公告)号：US20180120921A1

公开(公告)日：2018-05-03

申请号：US15726566

申请日：2017-10-06

Applicant: QUALCOMM Incorporated

Inventor： Shaul Yohai Yifrach ,  Amit Gil ,  James Lionel Panian ,  Ofer Rosenberg ,  Richard Dominic Wietfeldt

IPC: G06F1/32 ,  G06F13/40 ,  H04L12/931 ,  H01L23/29

CPC classification number: G06F1/3253 ,  G06F13/4072 ,  G06F13/4273 ,  G06F13/4291 ,  H01L23/291 ,  H04L49/40 ,  Y02D10/151

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.

公开(公告)号：US09949027B2

公开(公告)日：2018-04-17

申请号：US15087208

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Amit Gil ,  Oded Schnitzer

IPC: H04R29/00 ,  H04R3/00 ,  H03G3/34

CPC classification number: H04R3/007 ,  G06F3/165 ,  G06F13/38 ,  G10L19/012 ,  G10L19/167 ,  H03G3/341 ,  H03G3/348

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

公开(公告)号：US20180041614A1

公开(公告)日：2018-02-08

申请号：US15226429

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Tomer Rafael Ben-Chen ,  Amit Gil ,  Dan Gilboa Waizman ,  Deepak Jindal ,  Ayala Miller ,  Shaul Yohai Yifrach

IPC: H04L29/06 ,  H04L12/741

CPC classification number: H04L69/22 ,  H04L45/741 ,  H04L45/745 ,  H04L69/04 ,  H04L69/08 ,  H04L69/18 ,  H04L69/321

Abstract: Hardware-based packet processing circuitry is provided. In this regard, hardware-based packet processing circuitry includes header processing circuitry and payload processing circuitry. The hardware-based packet processing circuitry receives a header portion and a payload portion of an incoming packet in a first packet format. The header processing circuitry and the payload processing circuitry process the header portion and the payload portion to form a processed header portion and a processed payload portion, respectively. The hardware-based packet processing circuitry generates an outgoing packet in a second packet format based on the processed header portion and the processed payload portion. By processing the incoming packet separately in the header processing circuitry and the payload processing circuitry, it is possible to accelerate selected steps (e.g., ciphering/deciphering, compression/de-compression, checksum, etc.) of packet processing via dedicated hardware functional block(s), thus reducing computing resource requirement and overhead associated with software-based packet processing.

公开(公告)号：US09880748B2

公开(公告)日：2018-01-30

申请号：US14621874

申请日：2015-02-13

Applicant: QUALCOMM Incorporated

Inventor： Amit Gil ,  Assaf Shacham

IPC: G06F12/02 ,  G06F3/06 ,  G06F9/50 ,  G06F13/16

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/50 ,  G06F12/0246 ,  G06F13/1668 ,  G06F2212/1024 ,  G06F2212/7201 ,  G06F2212/7202

Abstract: Bifurcated memory management for memory elements techniques are disclosed. In one aspect, a memory element includes a self-managed portion and a portion that is managed by a remote host. Software that needs low latency access may be stored in the portion of the memory element that is managed by the remote host and other software may be stored in the portion of the memory element that is managed by the memory element. By providing such bifurcated memory management of the memory element, a relatively inexpensive memory element may be used to store software while at the same time allowing low latency (albeit at low throughputs) access to sensitive software elements with minimal bus logic.

公开(公告)号：US09552318B2

公开(公告)日：2017-01-24

申请号：US14295653

申请日：2014-06-04

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Henry Laurel Sanchez ,  Hung Quoc Vuong ,  Amit Gil

IPC: G06F12/02 ,  G06F13/40 ,  G06F13/42 ,  G11C16/14 ,  G11C16/34 ,  G11C16/20

CPC classification number: G06F13/4022 ,  G06F13/4068 ,  G06F13/4234 ,  G11C16/14 ,  G11C16/20 ,  G11C16/34

Abstract: Removable memory card type detection systems and methods are disclosed. In one aspect, a removable memory card is inserted into a receptacle of a host. The host determines a type of removable memory card based upon either electrical or physical properties of the removable memory card. In this manner, if the host detects that the removable memory card possesses certain electrical or physical properties associated with a microSD card, the host determines that the removable memory card is a microSD type card. If the host detects that the removable memory card possesses certain electrical or physical properties associated with a UFS card, the host determines that the removable memory card is a UFS type card. By determining the card type based on detection of certain electrical or physical properties, aspects disclosed herein are able to distinguish between UFS and microSD cards without requiring an additional pin or card initialization time.

Abstract translation: 公开了可移动存储卡型检测系统和方法。 在一个方面，将可移动存储卡插入到主机的插座中。 主机基于可移动存储卡的电气或物理属性来确定可移动存储卡的类型。 以这种方式，如果主机检测到可移动存储卡具有与microSD卡相关联的某些电气或物理属性，则主机确定可移动存储卡是microSD型卡。 如果主机检测到可移动存储卡具有与UFS卡相关联的某些电气或物理属性，则主机确定可移动存储卡是UFS型卡。 通过基于某些电气或物理特性的检测来确定卡类型，本文公开的方面能够区分UFS和microSD卡，而不需要额外的引脚或卡初始化时间。

公开(公告)号：US20160337257A1

公开(公告)日：2016-11-17

申请号：US14713028

申请日：2015-05-15

Applicant: QUALCOMM Incorporated

Inventor： Shaul Yohai Yifrach ,  Amit Gil

IPC: H04L12/863

CPC classification number: H04L47/6205 ,  H04L47/623 ,  H04L49/3027

Abstract: Aspects disclosed in the detailed description include head-of-line blocking (HOLB) mitigation in communication devices. Output queues employed by a communication device for transmitting data are susceptible to HOLB. In this regard, in one aspect, a queue monitoring logic is configured to detect HOLB by measuring and comparing a depth(s) of an output queue(s) against a queue-overflow threshold. If the depth(s) of the output queue(s) exceeds the queue-overflow threshold, a queue weight(s) of a corresponding input queue(s) is decreased to reduce data flow into the output queue(s), thus mitigating the HOLB in the output queue(s). In another aspect, the queue monitoring logic is configured to detect queue depletion by comparing the depth(s) of the output queue(s) against a queue-depletion threshold. By mitigating the HOLB and the data starvation in the output queue(s), it is possible to optimize the output queue(s) to achieve higher throughput and data integrity with lower power consumption.

Abstract translation: 在详细描述中公开的方面包括通信设备中的行前阻止（HOLB）抑制。 用于传输数据的通信设备使用的输出队列易受HOLB的影响。 在这方面，在一方面，队列监视逻辑被配置为通过测量和比较输出队列的深度与队列溢出阈值来检测HOLB。 如果输出队列的深度超过队列溢出阈值，则减少对应输入队列的队列权重以减少进入输出队列的数据流，从而减轻 输出队列中的HOLB。 在另一方面，队列监视逻辑被配置为通过将输出队列的深度与队列耗尽阈值进行比较来检测队列耗尽。 通过减轻输出队列中的HOLB和数据不足，可以优化输出队列，以便以更低的功耗实现更高的吞吐量和数据完整性。

公开(公告)号：US20160239218A1

公开(公告)日：2016-08-18

申请号：US14621874

申请日：2015-02-13

Applicant: QUALCOMM Incorporated

Inventor： Amit Gil ,  Assaf Shacham

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/50 ,  G06F12/0246 ,  G06F13/1668 ,  G06F2212/1024 ,  G06F2212/7201 ,  G06F2212/7202

Abstract: Bifurcated memory management for memory elements techniques are disclosed. In one aspect, a memory element includes a self-managed portion and a portion that is managed by a remote host. Software that needs low latency access may be stored in the portion of the memory element that is managed by the remote host and other software may be stored in the portion of the memory element that is managed by the memory element. By providing such bifurcated memory management of the memory element, a relatively inexpensive memory element may be used to store software while at the same time allowing low latency (albeit at low throughputs) access to sensitive software elements with minimal bus logic.

Abstract translation: 公开了用于存储器元件技术的分叉存储器管理。 在一个方面，存储元件包括自管理部分和由远程主机管理的部分。 需要低延迟访问的软件可以存储在由远程主机管理的存储器元件的部分中，并且其他软件可以存储在由存储器元件管理的存储器元件的部分中。 通过提供存储器元件的这种分叉存储器管理，可以使用相对便宜的存储器元件来存储软件，同时允许以最小总线逻辑访问敏感软件元件的低延迟（尽管在低吞吐量）。

公开(公告)号：US20140281283A1

公开(公告)日：2014-09-18

申请号：US13798803

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Assaf Shacham ,  Amit Gil ,  Erez Tsidon ,  Yanru Li ,  Azzedine Touzni

IPC: G11C7/10

CPC classification number: G11C7/1075 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/462 ,  G06F9/463 ,  G06F9/52 ,  G06F9/544 ,  G06F11/0757 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

Abstract: Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data.

Abstract translation: 描述了使用多端口共享非易失性存储器的有效技术，其减少了诸如调制解调器控制处理器之类的专用功能特定处理器的存储器访问中的延迟。 调制解调器处理器抢占正在从多端口共享非易失性存储器闪存器件访问数据的主处理器，允许调制解调器处理器快速访问闪存设备中的数据。 抢占过程使用由寻求访问并中断处理器被抢占的处理器发起的门铃中断。 抢占后，主机处理器可以恢复或重新启动数据访问。 处理器的访问控制利用硬件信号量原子控制机制。 共享的非易失性存储器模块的功率控制包括至少一个不活动定时器，以指示何时可以安全地减少或关闭共享的非易失性存储器模块的电源电压。 共享内存的任何处理器可能会重新启动电源，从而可以快速访问数据。

公开(公告)号：US11287842B2

公开(公告)日：2022-03-29

申请号：US16927657

申请日：2020-07-13

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Amit Gil ,  Shaul Yohai Yifrach

IPC: G06F1/12 ,  G06F13/42

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

公开(公告)号：US20220019548A1

公开(公告)日：2022-01-20

申请号：US16931826

申请日：2020-07-17

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Amit Gil ,  Navdeep Mer ,  Viney Kumar

IPC: G06F13/362 ,  G06F13/24 ,  G06F13/40 ,  G06F9/54

Abstract: Nested commands for a radio frequency front end (RFFE) bus are provided. In particular, timing commands may be nested inside a normal data flow. On receipt of a nested timing command, a slave on the RFFE bus suspends or halts an active command and addresses the timing command. On completion of the timing command, the slave returns to the halted command. By allowing such nested commands, counters in the slave that would otherwise be used to track triggers may be eliminated or reduced and power may be conserved by placing a clock signal associated with the bus into a low power mode.