公开(公告)号：US20160240437A1

公开(公告)日：2016-08-18

申请号：US15141198

申请日：2016-04-28

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Zhongze WANG ,  Niladri MOJUMDER ,  Mustafa BADAROGLU

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

公开(公告)号：US20160233126A1

公开(公告)日：2016-08-11

申请号：US15133040

申请日：2016-04-19

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  John Jianhong ZHU ,  Choh Fei YEAP

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76843 ,  H01L21/76831 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.

公开(公告)号：US20160225881A1

公开(公告)日：2016-08-04

申请号：US15097127

申请日：2016-04-12

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Choh Fei YEAP

IPC: H01L29/66 ,  H01L21/324 ,  H01L29/06 ,  H01L21/265 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L29/66803 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/0603 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods for fabricating a fin in a fin field effect transistor (FinFET), include exposing a single crystal fin structure coupled to a substrate of the FinFET. The single crystal fin structure is of a first material. The method further includes implanting a second material into the exposed single crystal fin structure at a first temperature. The first temperature reduces amorphization of the single crystal fin structure. The implanted single crystal fin structure comprises at least 20% of the first material. The method also includes annealing the implanted fin structure at a second temperature. The second temperature reduces crystal defects in the implanted fin structure to form the fin.

公开(公告)号：US20160093364A1

公开(公告)日：2016-03-31

申请号：US14499147

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook JUNG ,  Younghwi YANG ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: Systems and methods include a static random-access memory (SRAM) bit cell circuit having an access transistor configured to pass a read current to a storage node, the access transistor including an access transistor back gate. The access transistor back gate is biased to enable selective current boosting of the read current during a read operation.

Abstract translation: 系统和方法包括具有存取晶体管的静态随机存取存储器（SRAM）位单元电路，存取晶体管被配置为将读取电流传递到存储节点，存取晶体管包括存取晶体管背栅极。 存取晶体管背栅极被偏置以使得在读取操作期间读取电流的选择性电流升高。

公开(公告)号：US20160087070A1

公开(公告)日：2016-03-24

申请号：US14495562

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Vladimir MACHKAOUTSAN ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Mustafa BADAROGLU ,  Choh Fei YEAP

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66803 ,  H01L21/2254 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.

Abstract translation: 体硅（Si）的一部分形成为具有翅片基底的翅片，并且在散热片基底上形成有工艺中的翅片。 翅片基底是掺杂硅，而工艺中的鳍是硅锗（SiGe）。 工艺中的SiGe鳍具有源极区和漏极区。 硼原位掺杂到漏区并进入源区。 任选地，硼通过在漏极区域和源极区域上形成具有硼的外延层进行原位掺杂，以及驱动退火以在源极区域和漏极区域中扩散硼。

公开(公告)号：US20150325514A1

公开(公告)日：2015-11-12

申请号：US14274378

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan MOJUMDER ,  Zhongze WANG ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/11

CPC classification number: H01L27/1104 ,  H01L27/0207

Abstract: A static random access memory (SRAM) cell includes a first conductive layer including a wordline landing pad extending into a neighboring memory cell in an adjacent row of a memory array. The wordline landing pad in the first conductive layer is electrically isolated from all gate contacts of the neighboring memory cell. The SRAM cell also includes a second conductive layer including a wordline coupled to the wordline landing pad in the first conductive layer. The SRAM cell further includes a first via coupling a gate contact of a pass transistor gate in the SRAM cell to the wordline landing pad in the first conductive layer. The SRAM cell also includes a second via coupling the wordline landing pad and the wordline of the second conductive layer.

Abstract translation: 静态随机存取存储器（SRAM）单元包括第一导电层，其包括延伸到存储器阵列的相邻行中的相邻存储器单元的字线着陆焊盘。 第一导电层中的字线着陆焊盘与相邻存储器单元的所有栅极触点电隔离。 SRAM单元还包括第二导电层，其包括耦合到第一导电层中的字线着陆焊盘的字线。 SRAM单元进一步包括将SRAM单元中的通过晶体管栅极的栅极接触耦合到第一导电层中的字线着陆焊盘的第一通孔。 SRAM单元还包括耦合字线着陆焊盘和第二导电层的字线的第二通孔。

公开(公告)号：US20150317426A1

公开(公告)日：2015-11-05

申请号：US14498939

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Niladri Narayan MOJUMDER ,  Zhongze WANG ,  Choh Fei YEAP

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/505 ,  G06F2217/78 ,  G06F2217/84

Abstract: Integrated circuit (IC) technology design may include binning data paths of an IC device of a current technology node to bins based on a performance of each of the data paths. Each of the plurality of bins is mapped to a representative circuit unit data path configured according to a predetermined set of electrical and/or physical parameters. The representative circuit unit data paths are calibrated according to updated electrical and/or physical parameters to increase the performance of the representative circuit unit data paths to improve the performance of the IC device in an advanced technology node.

Abstract translation: 集成电路（IC）技术设计可以包括基于每个数据路径的性能来对当前技术节点的IC设备的分组数据路径进行分组。 多个箱中的每一个被映射到根据预定的一组电和/或物理参数配置的代表性电路单元数据路径。 代表性的电路单元数据路径根据更新的电和/或物理参数进行校准，以增加代表性电路单元数据路径的性能，以提高先进技术节点中的IC器件的性能。

公开(公告)号：US20150303145A1

公开(公告)日：2015-10-22

申请号：US14255820

申请日：2014-04-17

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  PR CHIDAMBARAM ,  Giridhar NALLAPATI ,  Choh Fei YEAP

IPC: H01L23/528 ,  H01L21/768 ,  G06F1/18

CPC classification number: H01L23/5283 ,  G06F1/18 ,  H01L21/76895 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates to a locally optimized integrated circuit (IC) including a first portion employing one or more metal interconnects having a first metal width and/or one or more vias having a first via width, and a second portion employing one or more metal interconnects having a second metal width and/or one or more vias having a second via width, wherein the second portion comprises a critical area of the IC, and wherein the second metal width is greater than the first metal width and the second via width is greater than the first via width. A method of locally optimizing an IC includes forming the one or more metal interconnects and/or the one or more vias in the first portion of the IC, and forming the one or more metal interconnects and/or the one or the more vias in the second portion of the integrated circuit.

Abstract translation: 本公开涉及局部优化的集成电路（IC），其包括使用具有第一金属宽度的一个或多个金属互连件的第一部分和/或具有第一通孔宽度的一个或多个通孔，以及采用一个或多个金属互连的第二部分 具有第二金属宽度和/或具有第二通孔宽度的一个或多个通孔，其中所述第二部分包括所述IC的临界区域，并且其中所述第二金属宽度大于所述第一金属宽度，并且所述第二通孔宽度更大 比第一个通道宽度。 局部优化IC的方法包括在IC的第一部分中形成一个或多个金属互连和/或一个或多个通孔，以及形成一个或多个金属互连和/或一个或多个通孔 集成电路的第二部分。

公开(公告)号：US20150301973A1

公开(公告)日：2015-10-22

申请号：US14484137

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Kern RIM ,  Stanley Seungchul SONG ,  Xiangdong CHEN ,  Raymond George Stephany ,  John Jianhong ZHU ,  Ohsang KWON ,  Esin TERZIOGLU ,  Choh Fei YEAP

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4221 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.

Abstract translation: 设计导电互连的方法包括至少部分地基于互连迹线间距和指定单元高度的整数倍来确定残余间隔值。 该方法还包括将剩余间隔分配到互连迹线间距内的至少一个互连迹线宽度或互连迹线空间。

公开(公告)号：US20150249155A1

公开(公告)日：2015-09-03

申请号：US14281660

申请日：2014-05-19

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Choh Fei YEAP

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02164 ,  H01L21/02238 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor fin is on a substrate, and extends in a longitudinal direction parallel to the substrate. The fin projects, in a vertical direction, to a fin top at a fin height above the substrate. An embedded fin stressor element is embedded in the fin. The fin stressor element is configured to urge a vertical compression force within the fin, parallel to the vertical direction. Optionally, the semiconductor material includes silicon, and embedded fin stressor element includes silicon dioxide.

Abstract translation: 半导体鳍片在基板上，并且在平行于基板的纵向方向上延伸。 翅片在垂直方向上突出到底板上方翅片高度的翅片顶部。 嵌入式翅片应力元件嵌入翅片。 翅片应力元件构造成促使平行于垂直方向的翅片内的垂直压缩力。 可选地，半导体材料包括硅，并且嵌入式翅片应力元件包括二氧化硅。