公开(公告)号：US20210183852A1

公开(公告)日：2021-06-17

申请号：US16712222

申请日：2019-12-12

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Haining YANG ,  Bin YANG

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8238

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate.

公开(公告)号：US20210082913A1

公开(公告)日：2021-03-18

申请号：US16569911

申请日：2019-09-13

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG

IPC: H01L27/088 ,  H01L23/535 ,  H01L21/762

Abstract: Certain aspects of the present disclosure generally relate to a single diffusion break having a conductive portion. An example semiconductor device generally includes a first semiconductor region, a second semiconductor region, a dielectric region, and a single diffusion break (SDB). The dielectric region is disposed between the first semiconductor region and the second semiconductor region. The SDB intersects at least one of the first semiconductor region or the second semiconductor region, and the SDB comprises an electrically conductive portion.

公开(公告)号：US20200035674A1

公开(公告)日：2020-01-30

申请号：US16277751

申请日：2019-02-15

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Haining YANG

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234

Abstract: A fin field effect transistors (FinFET) array includes a first transistor having a fin and a first conductive gate on the fin. The FinFET array also includes a second transistor having another fin and a second conductive gate on the other fin. The FinFET array further includes a first dielectric material and a self-aligned dielectric spacer. The first dielectric material is between the first transistor and the second transistor and on at least a portion of sidewalls of each of the first conductive gate and the second conductive gate. The self-aligned dielectric spacer is on at least a portion of the sidewalls of each of the first conductive gate and the second conductive gate.

公开(公告)号：US20160370699A1

公开(公告)日：2016-12-22

申请号：US15182510

申请日：2016-06-14

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Hyeokjin Bruce LIM ,  Ohsang KWON ,  Mickael MALABRY ,  Jingwei ZHANG ,  Raymond George STEPHANY ,  Haining YANG ,  Kern RIM ,  Stanley Seungchul SONG ,  Mukul GUPTA ,  Foua VANG

IPC: G03F1/70 ,  G06F17/50

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5068

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

Abstract translation: 在本公开的一个方面，提供了一种方法，计算机可读介质和用于分配多个图案化处理的特征颜色的装置。 该装置接收集成电路布局信息，该信息包括一组特征的集合，以及针对特征集合的第一特征集的每个特征的多种颜色的分配颜色。 另外，该装置对特征的第二子集执行颜色分解，以将颜色分配给第二特征子集中的特征。 特征的第二子集包括不包括在具有分配颜色的特征的第一子集中的特征集合中的特征。

公开(公告)号：US20160351677A1

公开(公告)日：2016-12-01

申请号：US14723199

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Haining YANG ,  Yanxiang LIU ,  Jeffrey Junhao XU

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/288

CPC classification number: H01L29/495 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.

Abstract translation: 在导体的上表面上生长牺牲帽。 电介质隔离物抵靠导体的一侧。 在绝缘帽的侧壁上形成上绝缘侧绝缘体。 选择性地蚀刻牺牲帽，留下盖子凹槽，并且上电介质侧隔片面向盖凹槽。 氮化硅填充在盖凹部中，以形成中心帽和具有中心盖和上部电介质间隔物的保护帽。

公开(公告)号：US20240404872A1

公开(公告)日：2024-12-05

申请号：US18327786

申请日：2023-06-01

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Haining YANG ,  Ming-Huei LIN

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L27/088 ,  H01L29/06

Abstract: Disclosed are devices that include a direct N/P local interconnect with minimal recess on shallow trench isolation (STI) oxide. This reduces undesirable coupling capacitance with active gate, which in turn improves AC performance of the device. Pull or even partial replacement of STI oxide with low-k dielectric can further reduce coupling capacitance.

公开(公告)号：US20240297218A1

公开(公告)日：2024-09-05

申请号：US18178248

申请日：2023-03-03

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong LIM ,  Hyunwoo PARK ,  Junjing BAO ,  Haining YANG

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a first gate structure disposed on a substrate and having a first channel length; a second gate structure disposed on the substrate and having the first channel length, a first source/drain space between the first gate structure and the second gate structure having a first distance; a third gate structure disposed on the substrate and having a second channel length; and a fourth gate structure disposed on the substrate and having the second channel length, a second source/drain space between the third gate structure and the fourth gate structure having a second distance. In an aspect, the second distance ranges from 0.75 times to 1.25 times the first distance.

公开(公告)号：US20240105797A1

公开(公告)日：2024-03-28

申请号：US17934400

申请日：2022-09-22

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Haining YANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  George Pete IMTHURN

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are apparatuses including transistor and methods for fabricating the same. The transistor may include a drain substantially enclosed in a drain silicide layer, wherein an integral drain via portion of the drain silicide layer is coupled to a second drain contact and wherein a first drain via couples the drain silicide layer to a first drain contact. The transistor may include a source substantially enclosed in a source silicide layer, wherein an integral source via portion of the source silicide layer is coupled to a second source contact and wherein a first source via couples the source silicide layer to a first source contact. The transistor may include a gate disposed between the source and the drain.

公开(公告)号：US20220173039A1

公开(公告)日：2022-06-02

申请号：US17107078

申请日：2020-11-30

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Haining YANG ,  Xia LI

IPC: H01L23/528 ,  H01L23/50 ,  H01L27/092 ,  H01L27/118

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with a buried power rail (BPR) having decreased resistance and a method of fabricating such a semiconductor device with a BPR. An example semiconductor device generally includes a substrate, a first transistor structure disposed above the substrate, a second transistor structure disposed above the substrate, and a BPR structure disposed between the first transistor structure and the second transistor structure. The BPR structure generally includes at least two distinguishable portions, which may be a first portion disposed above a second portion, the second portion having a greater width than the first portion.

公开(公告)号：US20210305250A1

公开(公告)日：2021-09-30

申请号：US16828487

申请日：2020-03-24

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  Xia LI ,  Bin YANG

IPC: H01L27/092 ,  H01L29/40 ,  H01L21/8238

Abstract: An integrated device that includes a substrate, a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, where the second gate contact is directly electrically coupled to only the gate.