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    Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets
    32.
    发明申请
    Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets 有权
    用于管理频率偏移系统中的多个时钟域的相位控制块

    公开(公告)号：US20150030113A1

    公开(公告)日：2015-01-29

    申请号：US14321723

    申请日：2014-07-01

    Applicant: Rambus Inc.

    Inventor： Hae-Chang Lee ,  Jared L. Zerbe ,  Carl William Werner

    IPC: H04L7/033 ,  H04L7/00

    CPC classification number: H04L7/0278 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/091 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0016 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337 ,  H04L7/0338

    Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

    Abstract translation: 用于根据接收到的数字信号30执行时钟恢复的电路。该电路至少包括用于对数字信号进行采样的边缘采样器105和数据采样器145以及时钟信号提供电路。 时钟信号供应电路提供边缘时钟25和数据时钟20信号，其相位偏移到边缘采样器105和数据采样器145的相应时钟输入。时钟信号供应电路可操作以选择性地改变相位偏移 边沿和数据时钟信号。

    EDGE BASED PARTIAL RESPONSE EQUALIZATION
    33.
    发明申请
    EDGE BASED PARTIAL RESPONSE EQUALIZATION 有权
    基于边缘部分响应均衡

    公开(公告)号：US20140016692A1

    公开(公告)日：2014-01-16

    申请号：US13932561

    申请日：2013-07-01

    Applicant: Rambus Inc.

    Inventor： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

    IPC: H04L25/03

    CPC classification number: H04L25/03057 ,  G06F13/38 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

    Abstract: A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

    Abstract translation: 设备实现基于边缘的部分响应判决反馈均衡的数据接收。 在一个示例性实施例中，该设备实现一个抽头权重适配器电路，其设置用于调整接收到的数据信号的抽头权重。 抽头重量适配器电路基于先前确定的数据值设置抽头权重，并使用一组边缘采样器从接收数据信号的边缘分析输入。 边缘分析可以包括通过由抽头权重适配器电路确定的抽头权重来调整采样的数据信号。 时钟发生电路产生边沿时钟信号，以控制由边缘采样器组执行的边缘采样。 可以根据边缘采样器的信号和由均衡器确定的先前数据值来生成边沿时钟信号。

    Phase control block for managing multiple clock domains in systems with frequency offsets
    37.
    发明授权
    Phase control block for managing multiple clock domains in systems with frequency offsets 有权

    公开(公告)号：US11063741B2

    公开(公告)日：2021-07-13

    申请号：US16659539

    申请日：2019-10-21

    Applicant: Rambus Inc.

    Inventor： Hae-Chang Lee ,  Jared LeVan Zerbe ,  Carl William Werner

    IPC: H04L7/027 ,  H03L7/081 ,  H03L7/091 ,  H04L7/033 ,  H04L7/00

    Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

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