公开(公告)号：US20190027489A1

公开(公告)日：2019-01-24

申请号：US15818146

申请日：2017-11-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi ORIMOTO ,  James KAI ,  Sayako Najamine ,  Takaaki Iwai ,  Shigeyuki Sugihara ,  Shuji Minagawa

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L29/06 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

公开(公告)号：US20180248013A1

公开(公告)日：2018-08-30

申请号：US15444725

申请日：2017-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Murshed CHOWDHURY ,  Andrew LIN ,  James KAI ,  Yanli ZHANG ,  Johann ALSMEIER

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L21/28158 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

Abstract: A trench having a uniform depth is provided in an upper portion of a semiconductor substrate. A continuous dielectric material layer is formed, which includes a gate dielectric that fills an entire volume of the trench. A gate electrode is formed over the gate dielectric such that the gate electrode overlies a center portion of the gate dielectric and does not overlie a first peripheral portion and a second peripheral portion of the gate dielectric that are located on opposing sides of the center portion of the gate dielectric. After formation of a dielectric gate spacer, a source extension region and a drain extension region are formed within the semiconductor substrate by doping respective portions of the semiconductor substrate.

公开(公告)号：US20180122906A1

公开(公告)日：2018-05-03

申请号：US15458272

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin YU ,  Kento KITAMURA ,  Tong ZHANG ,  Chun GE ,  Yanli ZHANG ,  Satoshi SHIMIZU ,  Yasuo KASAGI ,  Hiroyuki OGAWA ,  Daxin MAO ,  Kensuke YAMAGUCHI ,  Johann ALSMEIER ,  James KAI

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.

公开(公告)号：US20180097009A1

公开(公告)日：2018-04-05

申请号：US15286063

申请日：2016-10-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Johann ALSMEIER ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  James KAI

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/7926

Abstract: A layer stack including an alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of memory stack structures, backside trenches are formed through the layer stack. The sacrificial material layers are replaced with electrically conductive layers. Drain select level dielectric isolation structures are formed through drain select level of the stack after formation of the electrically conductive layers. The drain select level dielectric isolation structures laterally separate portions of conductive layers that are employed as drain select level gate electrodes for the memory stack structures.

公开(公告)号：US20170148808A1

公开(公告)日：2017-05-25

申请号：US15219652

申请日：2016-07-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi NISHIKAWA ,  Masafumi MIYAMOTO ,  James KAI

IPC: H01L27/115 ,  H01L29/06 ,  H01L21/311 ,  H01L23/528 ,  H01L21/28 ,  H01L29/08 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/0847

Abstract: An alternating stack of sacrificial material layers and insulating layers is formed over a substrate. Replacement of sacrificial material layers with electrically conductive layers can be performed employing a subset of openings. A predominant subset of the openings is employed to form memory stack structures therein. A minor subset of the openings is employed as access openings for introducing an etchant to remove the sacrificial material layers to form lateral recesses and to provide a reactant for depositing electrically conductive layers in the lateral recesses. By distributing the access openings across the entirety of the openings and eliminating the need to employ backside trenches for replacement of the sacrificial material layers, the size and lateral extent of backside trenches can be reduced to a level sufficient to accommodate only backside contact via structures.