公开(公告)号：US20180075919A1

公开(公告)日：2018-03-15

申请号：US15262262

申请日：2016-09-12

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Xuehong Yu ,  Yingda Dong ,  Nian Niles Yang

IPC: G11C16/34 ,  G11C16/28 ,  G11C16/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  H01L27/115

CPC classification number: G11C16/3495 ,  G11C7/14 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28 ,  G11C16/3445 ,  G11C16/349 ,  H01L27/1157 ,  H01L27/11582

Abstract: Techniques are provided for measuring the endurance of a set of data memory cells by evaluating the threshold voltage (Vth) of associated dummy memory cells. A cell has a high endurance or good data retention if it is able to maintain the charges. However, there can be a variation in the endurance of cells even within a single die. By evaluating the dummy memory cells, an early warning can be obtained of a degradation of the data memory cells. Moreover, there is no interference with the operation of the data memory cells. Based on a number of dummy memory cells which have a Vth below a demarcation voltage, a corrective action is taken such as adjusting read voltages, an initial program voltage and/or an initial erase voltage, or marking the block as being bad and recovering the data.

公开(公告)号：US20180033794A1

公开(公告)日：2018-02-01

申请号：US15221269

申请日：2016-07-27

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yanli Zhang ,  Raghuveer Makala ,  Yingda Dong

IPC: H01L27/115 ,  H01L27/105

CPC classification number: H01L27/1157 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.

公开(公告)号：US09859298B1

公开(公告)日：2018-01-02

申请号：US15190574

申请日：2016-06-23

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Jayavel Pachamuthu ,  Yingda Dong

IPC: H01L29/792 ,  H01L27/11582 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11568

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02667 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11568 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7926

Abstract: Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, rounding off of the control gate layers due to inadvertent oxidation during fabrication is avoided. An amorphous silicon layer is deposited along the sidewall of the memory holes, adjacent to the control gate layers. Si3N4 is deposited along the amorphous silicon layer and oxidized in the memory hole to form SiO2. The amorphous silicon layer acts as an oxidation barrier for the sacrificial material of the control gate layers. The amorphous silicon layer is subsequently oxidized to also form SiO2. The two SiO2 layers together form a blocking oxide layer.

公开(公告)号：US20170365349A1

公开(公告)日：2017-12-21

申请号：US15627738

申请日：2017-06-20

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Yingda Dong ,  Jiahui Yuan ,  Charles Kwong

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/20 ,  G11C16/24 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C2211/563

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. Countermeasures are provided for a first read situation in which a memory is read after a power on event or after a long delay since a last read. Read voltages of lower or higher programmed data states are set according to a positive or negative temperature coefficient (Tco), respectively. Read voltages for error recovery can be set similarly. In another aspect, a wait period between a dummy voltage and a read voltage is a function of temperature. In another aspect, word line voltages of unselected blocks are set according to a negative Tco. In another aspect, pass voltages are set based on a Tco for each programmed data state.

公开(公告)号：US20170345705A1

公开(公告)日：2017-11-30

申请号：US15163236

申请日：2016-05-24

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Yingda Dong ,  Jayavel Pachamuthu ,  Ching-Huang Lu

IPC: H01L21/768 ,  H01L27/1157 ,  H01L23/528 ,  H01L21/28 ,  H01L23/522 ,  H01L27/11582 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833

Abstract: Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, the memory device is provided with a reduced dielectric constant (k) in locations of a fringing electric field of the control gate. For example, portions of the dielectric layers can be replaced with a low-k material. One approach involves recessing the dielectric layer and providing a low-k material in the recess. Another approach involves doping a portion of the blocking oxide layer to reduce its dielectric constant. Another approach involves removing a portion of the blocking oxide layer. In another aspect, the memory device is provided with an increased dielectric constant adjacent to the control gates.

公开(公告)号：US20170345470A1

公开(公告)日：2017-11-30

申请号：US15163171

申请日：2016-05-24

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Vinh Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C7/14 ,  G11C7/04 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C7/14 ,  G11C7/04 ,  G11C7/062 ,  G11C7/22 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/1157 ,  H01L27/11582

Abstract: Techniques are provided for reducing program disturb and short term data retention loss. Program disturb becomes worse for the drain-side memory cells at higher temperatures, while data retention generally does not become worse at higher temperatures. In one aspect, a deeper erase is provided for drain-side memory cells when the temperature is relatively high, to reduce program disturb. In another aspect, the verify levels of the programmed data states are lowered to reduce data retention loss when the temperature is relatively high. In another aspect, the number of read errors is used to adjust the depth of the depth of the erase operation. In another aspect, a pass voltage of a drain-side cell is lowered during a verify test for another cell to account for the deep erase of the drain-side cell.

公开(公告)号：US09830963B1

公开(公告)日：2017-11-28

申请号：US15163171

申请日：2016-05-24

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Vinh Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C7/14 ,  G11C7/04 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C7/14 ,  G11C7/04 ,  G11C7/062 ,  G11C7/22 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/1157 ,  H01L27/11582

Abstract: Techniques are provided for reducing program disturb and short term data retention loss. Program disturb becomes worse for the drain-side memory cells at higher temperatures, while data retention generally does not become worse at higher temperatures. In one aspect, a deeper erase is provided for drain-side memory cells when the temperature is relatively high, to reduce program disturb. In another aspect, the verify levels of the programmed data states are lowered to reduce data retention loss when the temperature is relatively high. In another aspect, the number of read errors is used to adjust the depth of the depth of the erase operation. In another aspect, a pass voltage of a drain-side cell is lowered during a verify test for another cell to account for the deep erase of the drain-side cell.

公开(公告)号：US09673216B1

公开(公告)日：2017-06-06

申请号：US15212682

申请日：2016-07-18

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yingda Dong ,  Ching-huang Lu

IPC: H01L27/115 ,  H01L21/311 ,  H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/02063 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11556 ,  H01L27/1157

Abstract: Disclosed herein are methods of forming memory cell films in 3D memory. An opening having a sidewall may be formed through a stack of alternating layers of silicon oxide and silicon nitride. Bird's beaks may be formed in the silicon nitride at interfaces with the silicon oxide. In one aspect, bird's beaks are formed using a wet SiN etch. In one aspect, bird's beaks are formed by oxidizing SiN. A dilute hydrofluoric acid (DHF) clean may be performed within the opening after forming the bird's beaks in the silicon nitride. A memory cell film may be formed in the opening after performing the DHF clean. The memory cell film is straight, or nearly straight, from top to bottom in a memory hole. The memory cell film is not as susceptible to parasitic charge trapping as a memory cell film having a wavy contour. Therefore, neighbor WL interference may be reduced.