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    Semiconductor device and method for manufacturing semiconductor device
    31.
    发明授权
    Semiconductor device and method for manufacturing semiconductor device 有权
    半导体装置及半导体装置的制造方法

    公开(公告)号：US09443592B2

    公开(公告)日：2016-09-13

    申请号：US14330481

    申请日：2014-07-14

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi Kato ,  Yasuhiko Takemura ,  Tetsuhiro Tanaka ,  Takayuki Inoue ,  Toshihiko Takeuchi ,  Yasumasa Yamane ,  Shunpei Yamazaki

    IPC: H01L21/00 ,  G11C16/04 ,  G11C16/20 ,  H01L21/28 ,  H01L27/108 ,  H01L27/115

    CPC classification number: G11C16/0466 ,  G11C16/20 ,  H01L21/28282 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/11568

    Abstract: A manufacturing method of a semiconductor device in which the threshold is corrected is provided. In a semiconductor device including a plurality of transistors each includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit for supplying a signal to the gate electrode and a circuit for supplying a signal to the source or drain electrode are electrically separated from each other. The process is performed in the state where the potential of the former circuit is set higher than the potential of the latter circuit.

    Abstract translation: 提供了其中校正阈值的半导体器件的制造方法。 在包括多个晶体管的半导体器件中，每个包括半导体，与半导体电连接的源电极或漏电极，栅电极和栅电极与半导体之间的电荷陷阱层，电子被俘获在电荷陷阱层 通过进行热处理，同时保持栅电极的电位高于源电极或漏电极的电位1秒以上。 通过该过程，阈值增加并且Icut减小。 用于向栅电极提供信号的电路和用于向源电极或漏电极提供信号的电路彼此电分离。 该处理在前一电路的电位被设置为高于后一电路的电位的状态下执行。

    Semiconductor device
    32.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09397153B2

    公开(公告)日：2016-07-19

    申请号：US14486179

    申请日：2014-09-15

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tetsuhiro Tanaka ,  Toshihiko Takeuchi ,  Yasumasa Yamane

    IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/12

    CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/0607 ,  H01L29/12 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/78696

    Abstract: Provided is a semiconductor device having a structure with which a decrease in electrical characteristics that becomes more significant with miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film, a gate electrode overlapping with the first oxide semiconductor film, a first gate insulating film between the first oxide semiconductor film and the gate electrode, and a second gate insulating film between the first gate insulating film and the gate electrode. In the first gate insulating film, a peak appears at a diffraction angle 2θ of around 28° by X-ray diffraction. A band gap of the first oxide semiconductor film is smaller than a band gap of the first gate insulating film, and the band gap of the first gate insulating film is smaller than a band gap of the second gate insulating film.

    Abstract translation: 提供一种半导体器件，其具有可以抑制随着小型化而变得更显着的电特性的降低的结构。 半导体器件包括第一氧化物半导体膜，与第一氧化物半导体膜重叠的栅电极，第一氧化物半导体膜和栅极之间的第一栅极绝缘膜，以及在第一栅极绝缘膜和第二栅极绝缘膜之间的第二栅极绝缘膜 栅电极。 在第一栅极绝缘膜中，以衍射角2出现峰值; 通过X射线衍射测得约为28°。 第一氧化物半导体膜的带隙小于第一栅极绝缘膜的带隙，第一栅极绝缘膜的带隙小于第二栅极绝缘膜的带隙。

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