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475 条记录 (耗时 0.051 秒)

    Method for forming a horizontal surface spacer and devices formed thereby
    31.
    发明授权
    Method for forming a horizontal surface spacer and devices formed thereby 失效
    用于形成水平表面间隔物的方法和由此形成的装置

    公开(公告)号：US6100172A

    公开(公告)日：2000-08-08

    申请号：US182173

    申请日：1998-10-29

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

    IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L21/768 ,  H01L21/822 ,  H01L29/78 ,  H01L21/22 ,  H01L21/425 ,  H01L21/8234

    CPC分类号： H01L29/66613 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/76895 ,  H01L21/822 ,  H01L29/7835

    摘要： The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an implant. By conformally depositing the resist over a substrate having both vertical and horizontal surfaces, implanting the resist, and developing the resist, the resist is removed from the vertical surfaces while remaining on the horizontal surfaces. Thus, a self-aligned spacer is formed on the horizontal surfaces while the spacer material is removed from the vertical surfaces. This horizontal-surface spacer can then be used in further fabrication. The preferred method can be used in many different processes where there is exists a need to differentially process the vertical and horizontal surfaces of a substrate.

    摘要翻译： 本发明提供一种用于在水平表面上形成自对准间隔物的方法，同时从垂直表面移除间隔物材料。 优选的方法使用可以通过使用植入物使其不溶于显影剂的抗蚀剂。 通过在具有垂直和水平表面的基底上保形地沉积抗蚀剂，植入抗蚀剂并显影抗蚀剂，在保持在水平表面上的同时将抗蚀剂从垂直表面上除去。 因此，当从垂直表面移除间隔物材料时，在水平表面上形成自对准间隔物。 然后可以将该水平表面间隔件用于进一步制造。 优选的方法可以用于许多不同的工艺，其中存在需要对衬底的垂直和水平表面进行差异化处理。

    Microelectronic structure by selective deposition
    33.
    发明授权
    Microelectronic structure by selective deposition 有权
    微电子结构通过选择性沉积

    公开(公告)号：US08138100B2

    公开(公告)日：2012-03-20

    申请号：US12273908

    申请日：2008-11-19

    申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7851 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78645

    摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

    摘要翻译： finFET结构包括位于衬底上的半导体鳍片。 栅电极穿过半导体鳍片。 栅电极具有邻接其侧壁的间隔层。 间隔层不完全覆盖半导体鳍片的侧壁。 栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上，而不是在衬底的邻接表面上，使得间隔层不完全覆盖半导体的侧壁 鳍。 可以使用侧向生长方法制造其它微电子结构。

    MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION
    38.
    发明申请
    MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION 有权
    通过选择性沉积的微电子结构

    公开(公告)号：US20090072317A1

    公开(公告)日：2009-03-19

    申请号：US12273894

    申请日：2008-11-19

    申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7851 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78645

    摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

    摘要翻译： finFET结构包括位于衬底上的半导体鳍片。 栅电极穿过半导体鳍片。 栅电极具有邻接其侧壁的间隔层。 间隔层不完全覆盖半导体鳍片的侧壁。 栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上而不是在基底的相邻表面上，使得间隔层不完全覆盖 半导体鳍片 可以使用侧向生长方法制造其它微电子结构。

    METHODS FOR FORMING SELF-ALIGNED BORDERLESS CONTACTS FOR STRAIN ENGINEERED LOGIC DEVICES AND STRUCTURE THEREOF
    39.
    发明申请
    METHODS FOR FORMING SELF-ALIGNED BORDERLESS CONTACTS FOR STRAIN ENGINEERED LOGIC DEVICES AND STRUCTURE THEREOF 有权
    用于形成用于应变工程逻辑器件的自对准无边界接触的方法及其结构

    公开(公告)号：US20090057730A1

    公开(公告)日：2009-03-05

    申请号：US11850172

    申请日：2007-09-05

    申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66545 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method for forming a borderless contact for a semiconductor FET (Field Effect Transistor) device, the method comprising, forming a gate conductor stack on a substrate, forming spacers on the substrate, such that the spacers and the gate conductor stack partially define a volume above the gate conductor stack, wherein the spacers are sized to define the volume such that a stress liner layer deposited on the gate conductor stack substantially fills the volume, depositing a liner layer on the substrate, the spacers, and the gate conductor stack, depositing a dielectric layer on the liner layer, etching to form a contact hole in the dielectric layer, etching to form the contact hole in the liner layer, such that a portion of a source/drain diffusion area formed in the substrate is exposed and depositing contact metal in the contact hole.

    摘要翻译： 一种用于形成半导体FET（场效应晶体管）器件的无边界接触的方法，所述方法包括：在衬底上形成栅极导体堆叠，在衬底上形成间隔物，使得间隔物和栅极导体堆叠部分地限定体积 在栅极导体堆叠之上，其中间隔物的尺寸设定成限定体积，使得沉积在栅极导体堆叠上的应力衬垫层基本上填充体积，在衬底，间隔物和栅极导体堆叠上沉积衬垫层，沉积 衬底层上的电介质层，蚀刻以在电介质层中形成接触孔，蚀刻以在衬垫层中形成接触孔，使得在衬底中形成的源极/漏极扩散区域的一部分被暴露并沉积接触 接触孔中的金属。

    Phase Change Memory Cell with Vertical Transistor
    40.
    发明申请
    Phase Change Memory Cell with Vertical Transistor 有权
    具有垂直晶体管的相变存储单元

    公开(公告)号：US20090001337A1

    公开(公告)日：2009-01-01

    申请号：US11771457

    申请日：2007-06-29

    申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    IPC分类号： H01L21/336 ,  H01L21/06 ,  H01L29/02

    CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

    摘要： A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

    摘要翻译： 部分地通过形成下电极特征，岛，牺牲特征，栅极特征和相变特征来制造集成电路中的存储单元。 岛形成在下电极特征上并具有一个或多个侧壁。 它包括下掺杂特征，形成在下掺杂特征之上的中掺杂特征，以及形成在中掺杂特征之上的上掺杂特征。 牺牲特征形成在岛上方，而栅极特征沿着岛的每个侧壁形成。 栅极特征覆盖岛的中间掺杂特征的至少一部分，并且可操作以控制其中的电阻。 最后，相位特征至少部分地通过用相变材料代替牺牲特征的至少一部分而在岛上方形成。 响应于电信号的应用，相变材料可操作以在较低和较高的电阻状态之间切换。