公开(公告)号：US10910313B2

公开(公告)日：2021-02-02

申请号：US15948543

申请日：2018-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L27/088 ,  H01L23/535 ,  H01L23/528 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

Abstract: An integrated circuit including a series of field effect transistors. Each field effect transistor includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, and a drain contact on the drain region. Upper surfaces of the source and drain contacts are spaced below an upper surface of the gate by a depth.

公开(公告)号：US20200279811A1

公开(公告)日：2020-09-03

申请号：US16577591

申请日：2019-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Rwik Sengupta

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/50 ,  H01L23/522 ,  H01L23/532

Abstract: An integrated circuit (IC) apparatus and a method of forming a conductive material in a backside of an IC are provided. The IC apparatus includes a substrate including a frontside and a backside; at least one first insulating material deposited in the backside of the substrate in a form of a trench; a conductive material deposited in each of the at least one first insulating material; at least one second insulating material deposited on the conductive material to insulate the conductive material from the substrate; an epitaxial crystalline material grown on the frontside of the substrate; at least one semiconductor component formed in the epitaxial crystalline material; and at least one via formed in the substrate to connect the conductive material to the at least one semiconductor component.

公开(公告)号：US20200234881A1

公开(公告)日：2020-07-23

申请号：US16417346

申请日：2019-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Titash Rakshit ,  Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Palle

IPC: H01G4/12 ,  H01L29/51 ,  H01L29/78

Abstract: A circuit element. In some embodiments, the circuit element includes a first terminal, a second terminal, and a layered structure. The layered structure may include a first conductive layer connected to the first terminal, a first piezoelectric layer on the first conductive layer, a second piezoelectric layer on the first piezoelectric layer, and a second conductive layer connected to the second terminal. The first piezoelectric layer may have a first piezoelectric tensor and a first permittivity tensor, and the second piezoelectric layer may have a second piezoelectric tensor and a second permittivity tensor, one or both of the second piezoelectric tensor and a second permittivity tensor differing, respectively, from the first piezoelectric tensor and the first permittivity tensor.

公开(公告)号：US10586738B2

公开(公告)日：2020-03-10

申请号：US15877931

申请日：2018-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L21/225 ,  H01L21/268 ,  H01L21/324 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

Abstract: A method for providing a semiconductor device and the device so formed are described. A doped semiconductor layer is deposited on a semiconductor underlayer. At least a portion of the semiconductor underlayer is exposed. A dopant for the doped semiconductor layer is selected from a p-type dopant and an n-type dopant. An ultraviolet-assisted low temperature (UVLT) anneal of the doped semiconductor layer is performed in an ambient. The ambient is selected from an oxidizing ambient and a nitriding ambient. The oxidizing ambient is used for the n-type dopant. The nitriding ambient is used for the p-type dopant. A sacrificial layer is formed by the doped semiconductor layer during the UVLT anneal. The dopant is driven into the portion of the semiconductor underlayer from the doped semiconductor layer by the UVLT anneal, thereby forming a doped semiconductor underlayer. The sacrificial layer is then removed.

公开(公告)号：US20190318998A1

公开(公告)日：2019-10-17

申请号：US16453475

申请日：2019-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Harsono S. Simka ,  Ganesh Hegde ,  Joon Goo Hong ,  Rwik Sengupta ,  Mark S. Rodder

IPC: H01L23/00 ,  H01L23/522 ,  H01L27/02

Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. A first portion of the circuit elements are connected to a first portion of the connective components and are active. A the second portion of the circuit elements are connected to a second portion of the connective components and are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry is indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

公开(公告)号：US10312152B2

公开(公告)日：2019-06-04

申请号：US15818657

申请日：2017-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong ,  Seung Hun Lee ,  Pan Kwi Park ,  Seung Ryul Lee

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/66 ,  H01L27/04

Abstract: A CMOS circuit includes a partial GAA nFET and a partial GAA pFET. The nFET and the pFET each include a fin including a stack of nanowire-like channel regions and a dielectric separation region extending completely between first and second nanowire-like channel regions of the stack. The nFET and the pFET each also include a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions. The channel heights of the nanowire-like channel regions of the partial GAA nFET and the partial GAA pFET are different.

公开(公告)号：US20190131182A1

公开(公告)日：2019-05-02

申请号：US15877931

申请日：2018-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/225 ,  H01L21/268 ,  H01L21/324 ,  H01L21/02

Abstract: A method for providing a semiconductor device and the device so formed are described. A doped semiconductor layer is deposited on a semiconductor underlayer. At least a portion of the semiconductor underlayer is exposed. A dopant for the doped semiconductor layer is selected from a p-type dopant and an n-type dopant. An ultraviolet-assisted low temperature (UVLT) anneal of the doped semiconductor layer is performed in an ambient. The ambient is selected from an oxidizing ambient and a nitriding ambient. The oxidizing ambient is used for the n-type dopant. The nitriding ambient is used for the p-type dopant. A sacrificial layer is formed by the doped semiconductor layer during the UVLT anneal. The dopant is driven into the portion of the semiconductor underlayer from the doped semiconductor layer by the UVLT anneal, thereby forming a doped semiconductor underlayer. The sacrificial layer is then removed.

公开(公告)号：US10008583B1

公开(公告)日：2018-06-26

申请号：US15683304

申请日：2017-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Joon Goo Hong

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L29/417 ,  H01L29/40

CPC classification number: H01L29/6656 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/7848 ,  H01L29/78696

Abstract: A method of manufacturing a gate-all-around (GAA) nanosheet (NS) field effect transistor (FET) includes forming a stack on a substrate. The stack includes an alternating arrangement of conducting channel layers and non-uniform sacrificial regions. Each of the non-uniform sacrificial regions includes upper, middle, and lower sacrificial layers. The upper and lower sacrificial layers are configured to etch at a first etch rate and the middle sacrificial layer is configured to etch at a second etch rate greater than the first etch rate.

公开(公告)号：US20170338346A1

公开(公告)日：2017-11-23

申请号：US15342003

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a sacrificial epitaxial gate stressor is deposited on the fin, causing strain in the fin. SD structures are then formed to anchor the ends of the fin, and the sacrificial epitaxial gate stressor is removed.

公开(公告)号：US20140210017A1

公开(公告)日：2014-07-31

申请号：US14243358

申请日：2014-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongcheol Kim ,  Sooyeon Jeong ,  Joon Goo Hong ,  Dohyoung Kim ,  Yongjin Kim ,  Jin Wook Lee ,  Yoonhae Kim

IPC: H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/66545

Abstract: A semiconductor device and a method of forming the semiconductor device includes: forming gate electrodes on a semiconductor substrate and forming spacers on both side surfaces of the gate electrodes; forming capping patterns on the gate electrodes; and forming a metal contact between the gate electrodes. Each of the capping patterns is formed to have a width greater than a width of each of the gate electrodes.

Abstract translation: 半导体器件和形成半导体器件的方法包括：在半导体衬底上形成栅电极并在栅电极的两个侧表面上形成间隔物; 在栅电极上形成封盖图案; 以及在栅电极之间形成金属接触。 每个封盖图案形成为具有大于每个栅电极的宽度的宽度。