公开(公告)号：US09048138B2

公开(公告)日：2015-06-02

申请号：US14281482

申请日：2014-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-Chang Moon ,  Sung-Min Hwang ,  Woonkyung Lee

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L29/7926

Abstract: A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.

Abstract translation: 三维半导体存储器件具有层叠结构，其包括彼此绝缘的单元栅极和彼此横向分离的第一串选择栅极，延伸穿过第一串选择栅极的垂直有源图案，侧壁之间的多层电介质层 垂直有源图案和单元栅极之间以及垂直有源图案和第一串选择栅极的侧壁之间以及至少一个第一补充导电图案。 第一串选择栅极设置在单元栅极的最上面的单元栅极上。 每个垂直有源图案延伸穿过堆叠在第一串选择门下的每个单元门。 第一补充导电图案与第一串选择门之一的侧壁接触。

公开(公告)号：USRE50137E1

公开(公告)日：2024-09-17

申请号：US17586023

申请日：2022-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn Yun ,  Zhiliang Xia ,  Ahn-Sik Moon ,  Se-Jun Park ,  Joon-Sung Lim ,  Sung-Min Hwang

IPC: H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11582 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

公开(公告)号：US20240014157A1

公开(公告)日：2024-01-11

申请号：US18349017

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Ho Ahn ,  Ji Won Kim ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Suk Kang Sung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/535 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H10B41/27 ,  H10B43/27 ,  H01L2924/14511 ,  H01L2224/08145 ,  H01L2924/1431

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

公开(公告)号：US11296102B2

公开(公告)日：2022-04-05

申请号：US16858983

申请日：2020-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Woosung Yang ,  Joon-Sung Lim ,  Jiyoung Kim ,  Jiwon Kim

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  G11C5/06 ,  G11C5/02

Abstract: Disclosed is a three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, a stack including first and second stacks sequentially stacked on the substrate, the stack having a staircase structure on the connection region, each of the first and second stacks including conductive patterns vertically stacked on the substrate, and contact plugs disposed on the connection region and respectively coupled to the conductive patterns. A bottom surface of each contact plug is located between top and bottom surfaces of a corresponding conductive pattern. In each stack, a recess depth of each contact plug varies monotonically in a stacking direction of the conductive patterns, when measured from a top surface of a corresponding conductive pattern. The contact plugs coupled to an uppermost conductive pattern of the first stack and a lowermost conductive pattern of the second stack have discrete recess depths.

公开(公告)号：US11289504B2

公开(公告)日：2022-03-29

申请号：US16777776

申请日：2020-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Dong-Sik Lee ,  Sung-Min Hwang ,  Joon-Sung Lim

IPC: H01L27/11582 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522 ,  H01L21/28 ,  H01L29/66

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

公开(公告)号：US20190043881A1

公开(公告)日：2019-02-07

申请号：US15982216

申请日：2018-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungjoong Kim ,  Joon-Sung Lim ,  Sung-Min Hwang

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/66 ,  H01L29/423 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/6681

Abstract: A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column.

公开(公告)号：US20130295761A1

公开(公告)日：2013-11-07

申请号：US13933772

申请日：2013-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

IPC: H01L21/768

CPC classification number: H01L21/768 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.

Abstract translation: 提供一种三维半导体器件及其制造方法。 该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。 第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。 第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。 这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。

公开(公告)号：US20130161831A1

公开(公告)日：2013-06-27

申请号：US13771526

申请日：2013-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

IPC: H01L23/522

CPC classification number: H01L21/768 ,  H01L23/5226 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.

Abstract translation: 三维半导体器件可以包括在基板的布线和接触区域上包括布线和接触区域以及薄膜结构的基板。 薄膜结构可以包括在接触区域中限定梯形结构的多个交替布线层和层间绝缘层，使得每个布线层包括在接触区域中延伸超过其它布线层的接触表面 离衬底更远。 多个接触结构可以在垂直于衬底的表面的方向上延伸，其中每个接触结构电连接到相应的一个接线层的接触表面。 还讨论了相关方法。

公开(公告)号：US12232318B2

公开(公告)日：2025-02-18

申请号：US17726899

申请日：2022-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Ho Ahn ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Bum Kyu Kang ,  Sang Don Lee

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.

公开(公告)号：US20240312937A1

公开(公告)日：2024-09-19

申请号：US18671649

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Jiwon Kim ,  Jaeho Ahn ,  Joon-Sung Lim ,  Sukkang Sung

IPC: H01L23/00 ,  G11C16/08 ,  G11C16/10 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L24/08 ,  G11C16/08 ,  G11C16/10 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/08135 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.