公开(公告)号：US20210183757A1

公开(公告)日：2021-06-17

申请号：US17017638

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  Hyunkyu Kim ,  Jongbo Shim ,  Eunhee Jung ,  Kyoungsei Choi

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US20210050297A1

公开(公告)日：2021-02-18

申请号：US16849629

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd

Inventor： Jihwang Kim ,  Jeongmin Kang ,  Hyunkyu Kim ,  Jongbo Shim ,  Kyoungsei Choi

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package is provided including a package substrate. The package substrate includes a substrate pattern and a substrate insulation layer at least partially surrounding the substrate pattern. The package substrate has a groove. An external connection terminal is disposed below the package substrate. An embedded semiconductor device is disposed within the groove of the package substrate. The embedded semiconductor device includes a first substrate. A first active layer is disposed on the first substrate. A first chip pad is disposed on the first active layer. A buried insulation layer is disposed within the groove of the package substrate and at least partially surrounds at least a portion of a lateral surface of the embedded semiconductor device. A mounted semiconductor device is disposed on the package substrate and is connected to the package substrate and the embedded semiconductor device.

公开(公告)号：US09425111B2

公开(公告)日：2016-08-23

申请号：US14751626

申请日：2015-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Woo Park ,  Ji Hwang Kim ,  Jongbo Shim

IPC: H01L23/48 ,  H01L21/66 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L22/32 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/49816 ,  H01L25/065 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a package substrate; a semiconductor chip mounted on a top surface of the package substrate; a chip pad disposed on a bottom surface of the semiconductor chip to face the top surface of the package substrate, the chip pad including a connection pad and a measurement pad; and a chip bump including a first bump provided between the package substrate and the connection pad and a second bump provided between the package substrate and the measurement pad. An interconnection disposed within the package substrate is not connected to the second bump to be electrically isolated from the second bump.

Abstract translation: 半导体封装包括封装衬底; 安装在所述封装衬底的顶表面上的半导体芯片; 芯片焊盘，其设置在所述半导体芯片的底面上以面向所述封装基板的上表面，所述芯片焊盘包括连接焊盘和测量焊盘; 以及包括设置在封装基板和连接焊盘之间的第一凸起的芯片凸块和设置在封装基板和测量垫之间的第二凸块。 设置在封装基板内的互连件不与第二凸块连接以与第二凸块电隔离。

公开(公告)号：US12261093B2

公开(公告)日：2025-03-25

申请号：US17883726

申请日：2022-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Kim ,  Jongbo Shim ,  Hwanpil Park ,  Jangwoo Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

公开(公告)号：US12148729B2

公开(公告)日：2024-11-19

申请号：US17577653

申请日：2022-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jihwang Kim ,  Jongbo Shim

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package structure includes a package substrate; a semiconductor chip on the package substrate and electrically connected to the package substrate; an interposer substrate above the package substrate and the semiconductor chip, wherein the interposer substrate includes a cavity recessed inward from a lower surface thereof, wherein the semiconductor chip is positioned within the cavity, at least from a plan view; and an adhesive layer positioned inside and outside the cavity, wherein the adhesive layer is formed on all of upper and side surfaces of the semiconductor chip, or on the side surfaces of the semiconductor chip.

公开(公告)号：US12062605B2

公开(公告)日：2024-08-13

申请号：US18308433

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Hyunkyu Kim ,  Jongbo Shim ,  Eunhee Jung ,  Kyoungsei Choi

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/45 ,  H01L25/0657

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US20240079285A1

公开(公告)日：2024-03-07

申请号：US18316682

申请日：2023-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongmin Kang ,  Jongbo Shim ,  Ji-Yong Park ,  Choongbin Yim ,  Sungeun Pyo

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate, a first semiconductor chip on the first substrate, a molding layer on the first substrate and the first semiconductor chip and has a plurality of recesses, a plurality of substrate connection terminals on the first substrate and in the plurality of recesses, and a second semiconductor chip on the plurality of substrate connection terminals. The plurality of recesses and the plurality of substrate connection terminals are horizontally spaced apart from the first semiconductor chip. The molding layer is spaced apart from the second semiconductor chip.

公开(公告)号：US20240063181A1

公开(公告)日：2024-02-22

申请号：US18124183

申请日：2023-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyun Lee ,  Jiyong Park ,  Jongbo Shim ,  Choongbin Yim

IPC: H01L25/065 ,  H10B80/00 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H10B80/00 ,  H01L25/0655 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/08112 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32227 ,  H01L2224/48228 ,  H01L2924/1436 ,  H01L2924/1431

Abstract: A semiconductor package may include a package substrate having a first surface and a second surface vertically opposite to each other, a first mounting region and a second mounting region horizontally spaced apart from each other, and first and second semiconductor devices respectively mounted on the first and second mounting regions on the first surface of the package substrate. The package substrate may include wiring patterns electrically connected to the first and second semiconductor devices, dummy patterns electrically insulated from the first and second semiconductor devices, and a reinforcing structure that extends along perimeters of the first and second mounting regions on the first surface of the package substrate, and is bonded to at least portions of the dummy patterns.

公开(公告)号：US11876083B2

公开(公告)日：2024-01-16

申请号：US17407647

申请日：2021-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Kim ,  Ji Hwang Kim ,  Hwan Pil Park ,  Jongbo Shim

IPC: H01L23/02 ,  H01L25/10 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L25/105 ,  H01L21/4882 ,  H01L25/0655 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.

公开(公告)号：US11710673B2

公开(公告)日：2023-07-25

申请号：US17376883

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Dongwook Kim ,  Hyunki Kim ,  Jongbo Shim ,  Jihwang Kim ,  Sungkyu Park ,  Yongkwan Lee ,  Byoungwook Jang

IPC: H01L23/12 ,  H01L23/538

CPC classification number: H01L23/12 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package including a first package substrate, a first semiconductor chip on the first package substrate, a first conductive connector on the first package substrate and laterally spaced apart from the first semiconductor chip, an interposer substrate on the first semiconductor chip and electrically connected to the first package substrate through the first conductive connector, the interposer substrate including a first portion overlapping the first semiconductor chip and a plurality of upper conductive pads in the first portion, a plurality of spacers on a lower surface of the first portion of the interposer substrate and positioned so as not to overlap the plurality of upper conductive pads in a plan view, and an insulating filler between the interposer substrate and the first package substrate may be provided.