公开(公告)号：US09871145B2

公开(公告)日：2018-01-16

申请号：US15628699

申请日：2017-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo Ito ,  Daisuke Matsubayashi ,  Masaharu Nagai ,  Yoshiaki Yamamoto ,  Takashi Hamada ,  Yutaka Okazaki ,  Shinya Sasagawa ,  Motomu Kurata ,  Naoto Yamade

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L29/66 ,  H01L21/425 ,  H01L21/46 ,  H01L27/12

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

公开(公告)号：US20180006061A1

公开(公告)日：2018-01-04

申请号：US15708714

申请日：2017-09-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Tomoaki Moriwaka ,  Shinya Sasagawa ,  Takashi Ohtsuki

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/1255 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/7869

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

公开(公告)号：US09755081B2

公开(公告)日：2017-09-05

申请号：US14954155

申请日：2015-11-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yutaka Okazaki ,  Hidekazu Miyairi

IPC: H01L29/786 ,  H01L21/822 ,  H01L27/06 ,  H01L29/423

CPC classification number: H01L29/78606 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

Abstract: A structure is employed in which a first protective insulating layer; an oxide semiconductor layer over the first protective insulating layer; a source electrode and a drain electrode that are electrically connected to the oxide semiconductor layer; a gate insulating layer that is over the source electrode and the drain electrode and overlaps with the oxide semiconductor layer; a gate electrode that overlaps with the oxide semiconductor layer with the gate insulating layer provided therebetween; and a second protective insulating layer that covers the source electrode, the drain electrode, and the gate electrode are included. Furthermore, the first protective insulating layer and the second protective insulating layer each include an aluminum oxide film that includes an oxygen-excess region, and are in contact with each other in a region where the source electrode, the drain electrode, and the gate electrode are not provided.

公开(公告)号：US09343579B2

公开(公告)日：2016-05-17

申请号：US14279374

申请日：2014-05-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yutaka Okazaki

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78606 ,  H01L27/1052 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer filling a groove is surrounded by insulating layers including an aluminum oxide film containing excess oxygen. Excess oxygen contained in the aluminum oxide film is supplied to the oxide semiconductor layer, in which a channel is formed, by heat treatment in a manufacturing process of the semiconductor device. Moreover, the aluminum oxide film forms a barrier against oxygen and hydrogen, which inhibits the removal of oxygen from the oxide semiconductor layer surrounded by the insulating layers including an aluminum oxide film and the entry of impurities such as hydrogen in the oxide semiconductor layer. Thus, a highly purified intrinsic oxide semiconductor layer can be obtained. The threshold voltage is controlled effectively by gate electrode layers formed over and under the oxide semiconductor layer.

Abstract translation: 提供一种包含氧化物半导体并在保持良好的电气性能的同时小型化的半导体器件。 在半导体器件中，填充沟槽的氧化物半导体层由包含过量氧的氧化铝膜的绝缘层包围。 通过在半导体器件的制造工艺中的热处理，将氧化铝膜中含有的过量氧供给到形成有沟道的氧化物半导体层。 此外，氧化铝膜形成阻止氧和氢的阻挡，其阻止氧化物从包括氧化铝膜的绝缘层包围的氧化物半导体层中除去，并且在氧化物半导体层中进入诸如氢的杂质。 因此，可以获得高度纯化的本征氧化物半导体层。 通过在氧化物半导体层上形成的栅电极层有效地控制阈值电压。

公开(公告)号：US09252286B2

公开(公告)日：2016-02-02

申请号：US14284733

申请日：2014-05-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo Isobe ,  Yutaka Okazaki ,  Kazuya Hanaoka ,  Shinya Sasagawa ,  Motomu Kurata

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L27/108 ,  H01L27/11

CPC classification number: H01L27/1225 ,  H01L27/10879 ,  H01L27/1104 ,  H01L27/11521 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.

Abstract translation: 在栅极绝缘膜上形成与氧化物半导体膜重叠的第一导电膜，通过使用经受电子束曝光的抗蚀剂选择性蚀刻第一导电膜形成栅电极，在栅绝缘膜上形成第一绝缘膜 和栅电极，在栅电极未被露出的同时去除第一绝缘膜的一部分，在第一绝缘膜，抗反射膜，第一绝缘膜和栅极绝缘膜上形成防反射膜 使用经受电子束曝光的抗蚀剂选择性蚀刻，以及与氧化物半导体膜的一端接触的源极和与氧化物半导体膜的另一端接触的第一绝缘膜和漏电极的一端，以及 形成第一绝缘膜的另一端。

公开(公告)号：US20150179803A1

公开(公告)日：2015-06-25

申请号：US14571981

申请日：2014-12-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Akihisa Shimomura ,  Yuhei Sato ,  Yasumasa Yamane ,  Yoshitaka Yamamoto ,  Hideomi Suzawa ,  Tetsuhiro Tanaka ,  Yutaka Okazaki ,  Naoki Okuno ,  Takahisa Ishiyama

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/78606 ,  H01L29/78696

Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.

Abstract translation: 提供具有高导通电流的晶体管。 半导体器件包括含有过量氧的第一绝缘体，在第一绝缘体上的第一氧化物半导体，第一氧化物半导体上的第二氧化物半导体，在第二氧化物半导体之上并且彼此分离的第一导体和第二导体 与第一氧化物半导体的侧表面接触的第三氧化物半导体，第二氧化物半导体的顶表面和侧表面，第一导体的顶表面和第二导体的顶表面，第二绝缘体 第三氧化物半导体以及与第二绝缘体和第三氧化物半导体相对的第二氧化物半导体的顶表面和侧表面的第三导体。 第一氧化物半导体具有比第三氧化物半导体更高的透氧性。

公开(公告)号：US12183747B2

公开(公告)日：2024-12-31

申请号：US18436245

申请日：2024-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Tomoaki Moriwaka ,  Shinya Sasagawa ,  Takashi Ohtsuki

IPC: H01L29/66 ,  H01L21/768 ,  H01L27/12 ,  H01L29/786 ,  H01L23/532

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

公开(公告)号：US12046683B2

公开(公告)日：2024-07-23

申请号：US17861432

申请日：2022-07-11

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yutaka Okazaki ,  Akihisa Shimomura ,  Naoto Yamade ,  Tomoya Takeshita ,  Tetsuhiro Tanaka

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/7869

Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.

公开(公告)号：US11967649B2

公开(公告)日：2024-04-23

申请号：US17895126

申请日：2022-08-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko Takeuchi ,  Naoto Yamade ,  Yutaka Okazaki ,  Sachiaki Tezuka ,  Shunpei Yamazaki

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H01L29/792 ,  H10B12/00

CPC classification number: H01L29/78693 ,  H01L21/8234 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1255 ,  H01L29/792 ,  H10B12/00

Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.

公开(公告)号：US11245039B2

公开(公告)日：2022-02-08

申请号：US16378622

申请日：2019-04-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshinobu Asami ,  Yutaka Okazaki ,  Satoru Okamoto ,  Shinya Sasagawa

IPC: H01L29/786 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L21/475 ,  H01L29/66 ,  H01L21/4757 ,  H01L21/67 ,  C23C16/40 ,  C23C16/455 ,  H01L27/12

Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.