公开(公告)号：US20230178451A1

公开(公告)日：2023-06-08

申请号：US17944464

申请日：2022-09-14

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Hsin-Jou Lin ,  Lung-Yuan Wang ,  Feng Kao ,  Chiu-Ling Chen

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3677 ,  H01L25/105 ,  H01L23/3672 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/50 ,  H01L21/4882 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/16235 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2225/1076 ,  H01L2924/16151 ,  H01L2924/16196 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/16315

Abstract: A method of manufacturing an electronic package is provided, in which a package module including a routing structure is stacked on a carrier structure via a plurality of conductive elements, a heat dissipation member covers a part of a surface of the routing structure, and an electronic module is disposed on another part of the surface of the routing structure, so that the routing structure is formed with at least one heat dissipation pad bonded to the heat dissipation member, such that the heat energy of the electronic module and the package module can be dissipated via the heat dissipation pad and the heat dissipation member.

公开(公告)号：US20220005786A1

公开(公告)日：2022-01-06

申请号：US17481610

申请日：2021-09-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Feng Kao ,  Mao-Hua Yeh

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31

Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.

公开(公告)号：US11152331B2

公开(公告)日：2021-10-19

申请号：US16673078

申请日：2019-11-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Feng Kao ,  Mao-Hua Yeh

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31

Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.

公开(公告)号：US09905546B2

公开(公告)日：2018-02-27

申请号：US14211244

申请日：2014-03-14

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Shih-Hao Tung ,  Chang-Yi Lan ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chu-Huei Huang

IPC: H01L21/56 ,  H01L23/28 ,  H01L25/00 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.

公开(公告)号：US09646921B2

公开(公告)日：2017-05-09

申请号：US14255326

申请日：2014-04-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

公开(公告)号：US09343387B2

公开(公告)日：2016-05-17

申请号：US14452871

申请日：2014-08-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chu-Chi Hsu ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chia-Kai Shih ,  Shu-Huei Huang

IPC: H01L23/31 ,  H01L25/10 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13186 ,  H01L2224/16168 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/1017 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/19103 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and an electronic element having a plurality of conductive posts, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, and each of the conductive posts and the corresponding conductive bump form a conductive element. The present invention facilitates the stacking process through butt joint of the conductive posts and the metal balls of the conductive bumps.

Abstract translation: 提供一种封装封装（PoP）结构，其包括：具有多个导电凸块的封装基板，其中每个导电凸块具有覆盖金属球的金属球和焊料; 以及具有多个导电柱的电子元件，其中通过将导电柱相应地接合到导电凸块上，电子元件堆叠在封装衬底上，并且每个导电柱和相应的导电凸块形成导电元件。 本发明有助于通过导电柱和导电凸块的金属球的对接的堆叠过程。

公开(公告)号：US20150054150A1

公开(公告)日：2015-02-26

申请号：US14085101

申请日：2013-11-20

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Cheng-Hsu Hsiao ,  Lung-Yuan Wang

IPC: H01L23/00

CPC classification number: H01L25/105 ,  H01L21/561 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating a semiconductor package is disclosed, which includes: providing first and second packaging substrates, wherein a surface of the first packaging substrate has first conductive pads and first conductive posts formed on the first conductive pads, a surface of the second packaging substrate has second conductive pads and second conductive posts formed on the second conductive pads, and the surface of the second packaging substrate further has a semiconductor chip disposed thereon; disposing the first packaging substrate on the second packaging substrate in a manner that the first conductive posts correspond in position to and are electrically connected to the second conductive posts; and forming an encapsulant between the first and second packaging substrates for encapsulating the first and second conductive posts and the semiconductor chip, thereby effectively preventing solder bridging and increasing the product yield and reliability.

Abstract translation: 公开了一种制造半导体封装的方法，其包括：提供第一和第二封装基板，其中第一封装基板的表面具有形成在第一导电焊盘上的第一导电焊盘和第一导电柱，第二封装基板的表面 具有形成在第二导电焊盘上的第二导电焊盘和第二导电柱，并且第二封装衬底的表面还具有设置在其上的半导体芯片; 将所述第一包装基板设置在所述第二包装基板上，使得所述第一导电柱位于所述第二导电柱的位置并且与所述第二导电柱电连接; 以及在第一和第二封装基板之间形成密封剂，用于封装第一和第二导电柱和半导体芯片，从而有效地防止焊料桥接并提高产品的产率和可靠性。

公开(公告)号：US20140367850A1

公开(公告)日：2014-12-18

申请号：US14077771

申请日：2013-11-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L21/56 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/16238 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A stacked package and a method of fabricating the same are provided. The stacked package includes: a first package, having a first encapsulant, a first electrical connection structure formed on one surface of the first encapsulant, a plurality of first conductive pillars formed in the first encapsulant, and a first semiconductor chip disposed in the first encapsulant are electrically connected to the first electrical connection structure; and a second package stacked on the first package, wherein the second package has a second encapsulant, a second electrical connection structure formed on the second encapsulant, a second semiconductor, a chip disposed in the second encapsulant and electrically connected to the second electrical connection structure, and a plurality of second conductive pillars formed in the second encapsulant and electrically connected to the first electrical conduction pillars. The stacked package can provide a great number of inputs/outputs for electronic applications.

Abstract translation: 提供堆叠式封装及其制造方法。 堆叠式封装包括：第一封装，具有第一密封剂，形成在第一密封剂的一个表面上的第一电连接结构，形成在第一密封剂中的多个第一导电柱，以及设置在第一密封剂中的第一半导体芯片 电连接到第一电连接结构; 以及堆叠在所述第一封装上的第二封装，其中所述第二封装具有第二密封剂，形成在所述第二密封剂上的第二电连接结构，第二半导体，设置在所述第二密封剂中并电连接到所述第二电连接结构 以及形成在第二密封剂中并电连接到第一导电柱的多个第二导电柱。 堆叠封装可以为电子应用提供大量的输入/输出。