公开(公告)号：US20060292776A1

公开(公告)日：2006-12-28

申请号：US11167647

申请日：2005-06-27

申请人： Been-Yih Jin ,  Robert Chau ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Markus Kuhn ,  Marko Radosavlievic ,  M. Shaheed ,  Patrick Keys

发明人： Been-Yih Jin ,  Robert Chau ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Markus Kuhn ,  Marko Radosavlievic ,  M. Shaheed ,  Patrick Keys

IPC分类号： H01L21/8234 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7848

摘要： An NMOS transistor may be formed with a biaxially strained silicon upper layer having a thickness of greater than 500 Angstroms. The resulting NMOS transistor may have good performance and may exhibit reduced self-heating. A PMOS transistor may be formed with both a biaxially and uniaxially strained silicon germanium layer. A source substrate bias applied to both NMOS and PMOS transistors can enhance their performance.

摘要翻译： NMOS晶体管可以形成为具有大于500埃的厚度的双轴应变硅上层。 所得的NMOS晶体管可以具有良好的性能并且可以表现出减少的自热。 PMOS晶体管可以形成为双轴和单轴应变的硅锗层。 施加到NMOS和PMOS晶体管的源极衬底偏置可以提高其性能。

公开(公告)号：US20060205167A1

公开(公告)日：2006-09-14

申请号：US11078267

申请日：2005-03-11

申请人： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Brian Doyle ,  Robert Chau ,  Everett Wang ,  Philippe Matagne ,  Lucian Shifren ,  Been Jin ,  Mark Stettler ,  Martin Giles

发明人： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Brian Doyle ,  Robert Chau ,  Everett Wang ,  Philippe Matagne ,  Lucian Shifren ,  Been Jin ,  Mark Stettler ,  Martin Giles

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/8234

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  Y10S438/933

摘要： A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

摘要翻译： 晶体管可以由不同层的硅锗形成，具有梯度锗浓度的最低层和具有恒定锗浓度的上层，使得最底层具有Si 1-x Ge Ge > x 。 在PMOS侧，最高层可以是Si 1-y N y O y的形式。 源极和漏极可以由PMOS侧的Si 1-z N z z z的外延硅锗形成。 在一些实施例中，在PMOS器件中，x大于y且z大于x。 因此，PMOS器件可以在通道方向上具有单轴压应力和面内双轴压应力。 在某些情况下，应力的这种组合可能导致较高的移动性和增加的设备性能。

公开(公告)号：US20060001109A1

公开(公告)日：2006-01-05

申请号：US10883183

申请日：2004-06-30

申请人： Mohamad Shaheen ,  Brian Doyle ,  Suman Datta ,  Robert Chau ,  Peter Tolchinksy

发明人： Mohamad Shaheen ,  Brian Doyle ,  Suman Datta ,  Robert Chau ,  Peter Tolchinksy

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L21/76243 ,  H01L21/76254 ,  H01L21/76256 ,  H01L29/045 ,  H01L29/66772

摘要： A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.

公开(公告)号：US20050242406A1

公开(公告)日：2005-11-03

申请号：US11173443

申请日：2005-06-30

申请人： Scott Hareland ,  Robert Chau ,  Brian Doyle ,  Suman Datta ,  Been-Yih Jin

发明人： Scott Hareland ,  Robert Chau ,  Brian Doyle ,  Suman Datta ,  Been-Yih Jin

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

公开(公告)号：US20050073060A1

公开(公告)日：2005-04-07

申请号：US10679124

申请日：2003-10-02

申请人： Suman Datta ,  Brian Doyle ,  Robert Chau ,  Jack Kavalieros ,  Bo Zheng ,  Scott Hareland

发明人： Suman Datta ,  Brian Doyle ,  Robert Chau ,  Jack Kavalieros ,  Bo Zheng ,  Scott Hareland

IPC分类号： G11C11/412 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/423 ,  H01L29/786

CPC分类号： G11C11/412 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

摘要： The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.

公开(公告)号：US20100065888A1

公开(公告)日：2010-03-18

申请号：US11332189

申请日：2006-01-12

申请人： Mohamad A. Shaheen ,  Brian Doyle ,  Suman Datta ,  Robert S. Chau ,  Peter Tolchinksy

发明人： Mohamad A. Shaheen ,  Brian Doyle ,  Suman Datta ,  Robert S. Chau ,  Peter Tolchinksy

IPC分类号： H01L29/778

CPC分类号： H01L29/785 ,  H01L21/76243 ,  H01L21/76254 ,  H01L21/76256 ,  H01L29/045 ,  H01L29/66772

摘要： A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.

摘要翻译： 高迁移率半导体组件。 在一个示例性方面，高迁移率半导体组件包括具有位于第一衬底上的<110>晶面位置处的第一参考取向的第一衬底和形成在第一衬底顶部上的第二衬底。 第二衬底具有位于第二衬底上的<100>晶面位置处的第二参考取向，其中第一参考取向与第二参考取向对准。 在另一示例性方面，第二衬底具有位于第二衬底上的<110>晶面位置处的第二参考取向，其中第二衬底形成在第一衬底上，第二参考取向通过 约45度。

公开(公告)号：US20080151603A1

公开(公告)日：2008-06-26

申请号：US12072971

申请日：2008-02-28

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

IPC分类号： G11C11/34

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0541

摘要： A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

摘要翻译： 描述了具有源电极和漏电极的晶体管。 晶体管具有至少一个电耦合在源极和漏极之间的半导体碳纳米管。 晶体管具有在碳纳米管和栅电极之间含有一个或多个量子点的栅电极和电介质材料。

公开(公告)号：US20070262389A1

公开(公告)日：2007-11-15

申请号：US11828290

申请日：2007-07-25

申请人： Robert Chau ,  Suman Datta ,  Brian Doyle ,  Been-Yih Jin

发明人： Robert Chau ,  Suman Datta ,  Brian Doyle ,  Been-Yih Jin

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is then filled with a semiconductor material. The semiconductor material is then planarized with the remainder of the oxide layer and the remainder of the oxide layer is then removed. The semiconductor fins thus exposed are of uniform height to within a specified tolerance.

摘要翻译： 本发明的实施例提供了一种用于对绝缘体上硅晶体管制造实现均匀的硅体高度的方法。 对于一个实施例，在半导体衬底上设置牺牲氧化物层。 氧化层被蚀刻以形成沟槽。 然后用半导体材料填充沟槽。 然后将半导体材料与氧化物层的其余部分平坦化，然后除去氧化物层的其余部分。 这样暴露的半导体鳍片具有均匀的高度，在规定的公差范围内。

公开(公告)号：US20070231997A1

公开(公告)日：2007-10-04

申请号：US11395860

申请日：2006-03-31

申请人： Brian Doyle ,  Titash Rakshit ,  Robert Chau ,  Suman Datta ,  Justin Brask ,  Uday Shah

发明人： Brian Doyle ,  Titash Rakshit ,  Robert Chau ,  Suman Datta ,  Justin Brask ,  Uday Shah

IPC分类号： H01L21/8242

CPC分类号： H01L29/7853 ,  H01L29/66818

摘要： A multi-body thickness (MBT) field effect transistor (FET) comprises a silicon body formed on a substrate. The silicon body may comprise a wide section and a narrow section between the wide section and the substrate. The silicon body may comprise more than one pair of a wide section and a narrow section, each pair being located at a different height of the silicon body. The silicon body is surrounded by a gate material on three sides. The substrate may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The MBT-FET combines the advantages of a wide fin device and a narrow fin device.

摘要翻译： 多体厚度（MBT）场效应晶体管（FET）包括形成在衬底上的硅体。 硅体可以包括在宽部分和基底之间的宽的部分和窄的部分。 硅体可以包括多于一对宽的部分和窄的部分，每对位于硅体的不同高度处。 硅体由三面的栅极材料包围。 衬底可以是体硅衬底或绝缘体上硅（SOI）衬底。 MBT-FET结合了宽鳍片器件和窄鳍片器件的优点。

公开(公告)号：US20070148926A1

公开(公告)日：2007-06-28

申请号：US11321128

申请日：2005-12-28

申请人： Suman Datta ,  Jack Kavalieros ,  Justin Brask ,  Brian Doyle ,  Amlan Majumdar

发明人： Suman Datta ,  Jack Kavalieros ,  Justin Brask ,  Brian Doyle ,  Amlan Majumdar

IPC分类号： H01L21/04

CPC分类号： H01L21/26586 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A method for providing halo implants in a tri-gate structure is described. Implantation is performed at two different angels to assure a halo for the top transistor and a halo for the side transistors.

摘要翻译： 描述了一种用于在三栅极结构中提供晕轮植入物的方法。 植入在两个不同的天使进行，以确保顶部晶体管的光环和侧面晶体管的光晕。