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    Thick epitaxial silicon by grain reorientation annealing and applications thereof
    34.
    发明授权
    Thick epitaxial silicon by grain reorientation annealing and applications thereof 有权
    通过晶粒重定向退火的厚外延硅及其应用

    公开(公告)号：US07914619B2

    公开(公告)日：2011-03-29

    申请号：US12263889

    申请日：2008-11-03

    申请人： Joel P. de Souza ,  Keith E. Fogel ,  Daniel A. Inns ,  Devendra K. Sadana ,  Katherine L. Saenger

    发明人： Joel P. de Souza ,  Keith E. Fogel ,  Daniel A. Inns ,  Devendra K. Sadana ,  Katherine L. Saenger

    IPC分类号： C30B29/06

    CPC分类号： C30B29/06 ,  C23C16/24 ,  C23C16/56 ,  C30B1/02

    摘要： The invention provides a high temperature (about 1150° C. or greater) annealing process for converting thick polycrystalline Si layers on the order of 1 μm to 40 μm on a single crystal seed layer into thick single crystal Si layers having the orientation of the seed layer, thus allowing production of thick Si films having the quality of single crystal silicon at high rates and low cost of processing. Methods of integrating such high temperature processing into solar cell fabrication are described, with particular attention to process flows in which the seed layer is disposed on a porous silicon release layer. Another aspect pertains to the use of similar high temperature anneals for poly-Si grain growth and grain boundary passivation. A further aspect relates to structures in which these thick single crystal Si films and passivated poly-Si films are incorporated.

    摘要翻译： 本发明提供一种高温（约1150℃或更高）的退火工艺，用于将单晶种子层上的1μm至40μm量级的多晶硅层转化成具有种子取向的厚单晶Si层 从而允许以高速率生产具有单晶硅质量的厚Si薄膜，并且处理成本低。 描述了将这种高温处理集成到太阳能电池制造中的方法，特别注意种子层设置在多孔硅释放层上的工艺流程。 另一方面涉及对于多晶硅晶粒生长和晶界钝化使用类似的高温退火。 另一方面涉及其中结合有这些厚单晶Si膜和钝化多晶硅膜的结构。

    THICK EPITAXIAL SILICON BY GRAIN REORIENTATION ANNEALING AND APPLICATIONS THEREOF
    35.
    发明申请
    THICK EPITAXIAL SILICON BY GRAIN REORIENTATION ANNEALING AND APPLICATIONS THEREOF 有权
    通过颗粒重新形成的厚度大的外延硅及其应用

    公开(公告)号：US20100112792A1

    公开(公告)日：2010-05-06

    申请号：US12263889

    申请日：2008-11-03

    申请人： Joel P. de Souza ,  Keith E. Fogel ,  Daniel A. Inns ,  Devendra K. Sadana ,  Katherine L. Saenger

    发明人： Joel P. de Souza ,  Keith E. Fogel ,  Daniel A. Inns ,  Devendra K. Sadana ,  Katherine L. Saenger

    IPC分类号： H01L21/205

    CPC分类号： C30B29/06 ,  C23C16/24 ,  C23C16/56 ,  C30B1/02

    摘要： The invention provides a high temperature (about 1150° C. or greater) annealing process for converting thick polycrystalline Si layers on the order of 1 μm to 40 μm on a single crystal seed layer into thick single crystal Si layers having the orientation of the seed layer, thus allowing production of thick Si films having the quality of single crystal silicon at high rates and low cost of processing. Methods of integrating such high temperature processing into solar cell fabrication are described, with particular attention to process flows in which the seed layer is disposed on a porous silicon release layer. Another aspect pertains to the use of similar high temperature anneals for poly-Si grain growth and grain boundary passivation. A further aspect relates to structures in which these thick single crystal Si films and passivated poly-Si films are incorporated.

    摘要翻译： 本发明提供一种高温（约1150℃或更高）的退火工艺，用于将单晶种子层上的1μm至40μm量级的多晶硅层转化成具有种子取向的厚单晶Si层 从而允许以高速率生产具有单晶硅质量的厚Si薄膜，并且处理成本低。 描述了将这种高温处理集成到太阳能电池制造中的方法，特别注意种子层设置在多孔硅释放层上的工艺流程。 另一方面涉及对于多晶硅晶粒生长和晶界钝化使用类似的高温退火。 另一方面涉及其中结合有这些厚单晶Si膜和钝化多晶硅膜的结构。

    High-quality SGOI by annealing near the alloy melting point
    36.
    发明授权
    High-quality SGOI by annealing near the alloy melting point 失效
    高品质SGOI通过在合金熔点附近退火

    公开(公告)号：US07679141B2

    公开(公告)日：2010-03-16

    申请号：US12027561

    申请日：2008-02-07

    申请人： Stephen W. Bedell ,  Huajie Chen ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Richard J. Murphy ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Huajie Chen ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Richard J. Murphy ,  Devendra K. Sadana

    IPC分类号： H01L31/392

    CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76254 ,  H01L29/1054

    摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.

    摘要翻译： 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。 在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。 该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

    Use of thin SOI to inhibit relaxation of SiGe layers
    37.
    发明授权
    Use of thin SOI to inhibit relaxation of SiGe layers 有权
    使用薄SOI抑制SiGe层的弛豫

    公开(公告)号：US06989058B2

    公开(公告)日：2006-01-24

    申请号：US10654232

    申请日：2003-09-03

    申请人： Stephen W. Bedell ,  Huajie Chen ,  Keith E. Fogel ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Huajie Chen ,  Keith E. Fogel ,  Devendra K. Sadana

    IPC分类号： C30B25/02

    CPC分类号： H01L21/7624 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/24917

    摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.

    摘要翻译： 在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化 温度。 因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。

    Method of measuring crystal defects in thin Si/SiGe bilayers
    40.
    发明授权
    Method of measuring crystal defects in thin Si/SiGe bilayers 失效
    测量薄Si / SiGe双层晶体缺陷的方法

    公开(公告)号：US06803240B1

    公开(公告)日：2004-10-12

    申请号：US10654231

    申请日：2003-09-03

    申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

    IPC分类号： H01L21302

    CPC分类号： G01N21/9501 ,  G01N21/9505 ,  G01N2021/8461

    摘要： Described herein is a method for delineating crystalline defects in a thin Si layer over a SiGe alloy layer. The method uses a defect etchant with a high-defect selectivity in Si. The Si is etched downed to a thickness that allows the defect pits to reach the underlying SiGe layer. A second etchant, which can be the same or different from the defect etchant, is then used which attacks the SiGe layer under the pits while leaving Si intact.

    摘要翻译： 这里描述了一种在SiGe合金层上描绘薄Si层中的晶体缺陷的方法。 该方法在Si中具有高缺陷选择性的缺陷蚀刻剂。 将Si蚀刻到允许缺陷凹坑到达下面的SiGe层的厚度。 然后使用可以与缺陷蚀刻剂相同或不同的第二蚀刻剂，其在凹陷下攻击SiGe层，同时保持Si完整。