公开(公告)号：US20200090997A1

公开(公告)日：2020-03-19

申请号：US16686682

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ling-Fu Nieh ,  Chun-Wei Hsu ,  Pinlei Edmund Chu ,  Chi-Jen Liu ,  Liang-Guang Chen ,  Yi-Sheng Lin

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L29/417 ,  H01L21/321 ,  H01L21/8238 ,  H01L23/485 ,  H01L29/08 ,  C09G1/02

Abstract: A method of manufacturing a device includes exposing at least one of a source/drain contact plug or a gate contact plug to a metal ion source solution during a manufacturing process, wherein a constituent metal of a metal ion in the metal ion source solution and the at least one source/drain contact plug or gate contact plug is the same. If the source/drain contact plug or the gate contact plug is formed of cobalt, the metal ion source solution includes a cobalt ion source solution. If the source/drain contact plug or the gate contact plug is formed of tungsten, the metal ion source solution includes a tungsten ion source solution.

公开(公告)号：US20190103308A1

公开(公告)日：2019-04-04

申请号：US15939894

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Ling-Fu Nieh ,  Pinlei Edmund Chu ,  Chi-Jen Liu ,  Yi-Sheng Lin ,  Ting-Hsun Chang ,  Chia-Wei Ho ,  Liang-Guang Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of forming are provided. In some embodiments the method includes forming a dielectric layer over a substrate and patterning the dielectric layer to form a first recess. The method may also include depositing a first layer in the first recess and depositing a second layer over the first layer, the second layer being different than the first layer. The method may also include performing a first chemical mechanical polish (CMP) process on the second layer using a first oxidizer and performing a second CMP process on remaining portions of the second layer and the first layer using the first oxidizer. The method may also include forming a first conductive element over the remaining portions of the first layer after the second CMP polish is performed.

公开(公告)号：US20170341201A1

公开(公告)日：2017-11-30

申请号：US15165902

申请日：2016-05-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Chi-Jen Liu ,  Liang-Guang Chen ,  Chih-Chung Chang ,  Cheng-Chun Chang ,  Hsin-Kai Chen ,  Yi-Sheng Lin ,  Shi-Ya Hsu ,  Tsung-Ju Lin ,  Yi-Sheng Ma

IPC: B24B37/32 ,  B24B37/20

CPC classification number: B24B37/32 ,  B24B37/20

Abstract: An embodiment retainer ring includes an outer ring encircling an opening and an inner ring attached to the outer ring. The inner ring is disposed between the opening and the outer ring. The inner ring includes a softer material than the outer ring and a plurality of voids within the softer material.

公开(公告)号：US20170221700A1

公开(公告)日：2017-08-03

申请号：US15492034

申请日：2017-04-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/02 ,  H01L21/288 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/401 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

公开(公告)号：US09449841B2

公开(公告)日：2016-09-20

申请号：US14134914

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Chi-Jen Liu ,  Ying-Liang Chuang ,  Li-Chieh Wu ,  Liang-Guang Chen ,  Ming-Liang Yen

IPC: H01L21/02 ,  H01L21/321 ,  H01L29/66 ,  H01L21/67

CPC classification number: H01L21/28123 ,  B24B37/20 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/67051 ,  H01L29/66545

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor structure including a metal gate (MG) layer formed to fill in a trench between two adjacent interlayer dielectric (ILD) regions; performing a chemical mechanical polishing (CMP) process using a CMP system to planarize the MG layer and the ILD regions; and cleaning the planarized MG layer using a O3/DIW solution including ozone gas (O3) dissolved in deionized water (DIW). The MG layer is formed on the ILD regions.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供包括形成为填充两个相邻层间电介质（ILD）区域之间的沟槽的金属栅极（MG）层的半导体结构; 使用CMP系统进行化学机械抛光（CMP）处理以使MG层和ILD区域平坦化; 以及使用溶解在去离子水（DIW）中的包含臭氧气体（O 3）的O 3 / DIW溶液清洗平坦化的MG层。 MG层形成在ILD区域上。

公开(公告)号：US09209272B2

公开(公告)日：2015-12-08

申请号：US14024247

申请日：2013-09-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Jen Liu ,  Li-Chieh Wu ,  Shich-Chang Suen ,  Liang-Guang Chen

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76895 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen.

Abstract translation: 一种方法包括在晶片的表面上形成晶体管的虚拟栅极，去除虚拟栅极，并将金属材料填充到由去除的虚拟栅极留下的沟槽中。 然后对金属材料进行化学机械抛光（CMP），其中金属材料的剩余部分形成晶体管的金属栅极。 在CMP之后，使用包含氯和氧的氧化 - 蚀刻剂在金属栅极的暴露的顶表面上进行处理。

公开(公告)号：US20150179432A1

公开(公告)日：2015-06-25

申请号：US14134914

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Chi-Jen Liu ,  Ying-Liang Chuang ,  Li-Chieh Wu ,  Liang-Guang Chen ,  Ming-Liang Yen

IPC: H01L21/02 ,  H01L21/306

CPC classification number: H01L21/28123 ,  B24B37/20 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/67051 ,  H01L29/66545

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor structure including a metal gate (MG) layer formed to fill in a trench between two adjacent interlayer dielectric (ILD) regions; performing a chemical mechanical polishing (CMP) process using a CMP system to planarize the MG layer and the ILD regions; and cleaning the planarized MG layer using a O3/DIW solution including ozone gas (O3) dissolved in deionized water (DIW). The MG layer is formed on the ILD regions.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供包括形成为填充两个相邻层间电介质（ILD）区域之间的沟槽的金属栅极（MG）层的半导体结构; 使用CMP系统进行化学机械抛光（CMP）处理以使MG层和ILD区域平坦化; 以及使用溶解在去离子水（DIW）中的包含臭氧气体（O 3）的O 3 / DIW溶液清洗平坦化的MG层。 MG层形成在ILD区域上。