公开(公告)号：US11676961B2

公开(公告)日：2023-06-13

申请号：US17086421

申请日：2020-11-01

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Yanbiao Pan

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823418 ,  H01L21/823437

Abstract: A semiconductor device includes a resistor having a resistor body including polysilicon, with fluorine in the polysilicon. The resistor body has a laterally alternating distribution of silicon grain sizes. The semiconductor device further includes an MOS transistor having a gate including polysilicon with fluorine. The fluorine in the gate has a higher average concentration than the fluorine in the resistor body. The semiconductor device may be formed by forming a gate/resistor layer including polysilicon. A fluorine implant mask is formed over the gate/resistor layer, exposing the gate/resistor layer in an area for the gate and over implant segments in an area for the resistor body. The implant segments do not cover the entire area for the resistor body. Fluorine is implanted into the gate/resistor layer where exposed by the fluorine implant mask. The gate/resistor layer is patterned to form the gate and the resistor body.

公开(公告)号：US20220375856A1

公开(公告)日：2022-11-24

申请号：US17489910

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Yuguo Wang ,  Haowen Bu

IPC: H01L23/522 ,  H01L23/525 ,  H01L21/70 ,  H01L21/283

Abstract: A method and an electronic device that includes an isolation structure having a dielectric material on or in a semiconductor surface layer, and a passive circuit component having a metal silicide structure on a side of the isolation structure, there the metal silicide structure includes a metal silicide portion and a dielectric portion, the dielectric portion of the metal silicide structure including one of silicon nitride, silicon oxide, silicon carbide, silicon carbon nitride, and silicon oxynitride. The method includes forming a dielectric material of the isolation structure on or in the semiconductor surface layer, forming a silicon-rich dielectric layer on a side of the isolation structure, and siliciding the silicon-rich dielectric layer to form the metal silicide structure on the side of the isolation structure.

公开(公告)号：US20220189954A1

公开(公告)日：2022-06-16

申请号：US17117421

申请日：2020-12-10

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Edward Hornung

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/225 ,  H01L21/8234

Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

公开(公告)号：US20200279905A1

公开(公告)日：2020-09-03

申请号：US16800002

申请日：2020-02-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar

IPC: H01L49/02 ,  H01L23/525 ,  H01L27/06 ,  H01L21/8234

Abstract: An integrated circuit includes a polysilicon resistor having a plurality of segments, including first, second and third segments, the second segment located between and running about parallel to the first and third segments. A first header connects the first and second segments, and a second header connects the second and third segments. A first metal silicide layer located over the first header extends over the first and second segments toward the second header. A second metal silicide layer located over the second header extends over the second and third segments toward the first header. A dielectric layer is located over and contacts the first, second and third segments between the first and second metal silicide layers.

公开(公告)号：US10276684B2

公开(公告)日：2019-04-30

申请号：US15372512

申请日：2016-12-08

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Steve Lytle

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06

Abstract: An integrated circuit may include a metal gate which extends over an active area and onto an isolation dielectric layer. A conductive spline is formed on the metal gate, extending on the metal gate over at least a portion of the isolation dielectric layer, and extending on the metal gate for a length at least four times a width of the metal gate.

公开(公告)号：US20170358659A1

公开(公告)日：2017-12-14

申请号：US15686449

申请日：2017-08-25

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Mahalingam Nandakumar

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/3105 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/423 ,  H01L21/32 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/7833

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench

公开(公告)号：US09564427B2

公开(公告)日：2017-02-07

申请号：US14996360

申请日：2016-01-15

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L27/06 ,  H01L29/49 ,  H01L29/872 ,  H01L29/47 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L27/0629 ,  H01L29/36 ,  H01L29/47 ,  H01L29/4966 ,  H01L29/66143 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/872

Abstract: An integrated circuit and method with a metal gate transistor and with a Schottky diode where the metal used to form the Schottky diode is the metal used to form the metal gate.

Abstract translation: 具有金属栅极晶体管和肖特基二极管的集成电路和方法，其中用于形成肖特基二极管的金属是用于形成金属栅极的金属。

公开(公告)号：US09455252B2

公开(公告)日：2016-09-27

申请号：US14875274

申请日：2015-10-05

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L21/425 ,  H01L27/07 ,  H01L21/265 ,  H01L21/8234 ,  H01L27/06 ,  H01L21/225 ,  H01L21/8238 ,  H01L49/02

CPC classification number: H01L27/0738 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/0629 ,  H01L28/20

Abstract: An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with effective channel length control, annealing the PSD implant, and subsequently concurrently implanting boron into a polysilicon resistor with a zero temperature coefficient of resistance using an implant mask which also exposes the PMOS transistor, followed by a millisecond anneal.

公开(公告)号：US09269636B2

公开(公告)日：2016-02-23

申请号：US14575490

申请日：2014-12-18

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Hiroaki Niimi

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092

CPC classification number: H01L21/823857 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/0922 ,  H01L29/66545 ,  H01L29/6659

Abstract: A replacement metal gate transistor is formed with high quality gate dielectric under the high-k dielectric. The high quality gate dielectric is formed on the substrate at a temperature of at least 850° C. A sacrificial gate dielectric is formed on the high quality gate dielectric and a polysilicon replacement gate is formed on the sacrificial gate dielectric. The polysilicon replacement gate is removed leaving a gate trench. The sacrificial gate dielectric is removed from a bottom of the gate. A high-k dielectric is deposited into the gate trench. Metal gate material is deposited on the high-k dielectric.

Abstract translation: 在高k电介质下形成具有高质量栅极电介质的替代金属栅极晶体管。 在至少850℃的温度下在衬底上形成高质量的栅极电介质。在高质量栅极电介质上形成牺牲栅极电介质，并且在牺牲栅极电介质上形成多晶硅替代栅极。 去除多晶硅替代栅极留下栅极沟槽。 从栅极的底部去除牺牲栅极电介质。 高k电介质沉积到栅极沟槽中。 金属栅极材料沉积在高k电介质上。

公开(公告)号：US20150187771A1

公开(公告)日：2015-07-02

申请号：US14578732

申请日：2014-12-22

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Mahalingam Nandakumar

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/28 ,  H01L21/321 ,  H01L29/51 ,  H01L21/027

CPC classification number: H01L27/092 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

Abstract translation: 一种具有金属栅极NMOS晶体管的集成电路和方法，其在高质量热生长界面电介质上具有高k第一栅极电介质，并且具有在化学生长界面电介质上具有高k最后栅极电介质的金属栅极PMOS晶体管。