公开(公告)号：US10162641B2

公开(公告)日：2018-12-25

申请号：US15429205

申请日：2017-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/312 ,  G06F12/12 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/10

Abstract: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

公开(公告)号：US20160357210A1

公开(公告)日：2016-12-08

申请号：US14733456

申请日：2015-06-08

Applicant: Texas Instruments Incorporated

Inventor： Michael Gill ,  Ramakrishnan Venkatasubramanian ,  Shane Stelmach ,  Jose Luis Flores

IPC: G05F3/02 ,  H03K17/687

CPC classification number: G05F3/02 ,  H03K17/6872 ,  H03K19/0016

Abstract: A power supply for an electronic circuit enables a low effort retention mode. During a normal mode a circuit module is supplied a first voltage sufficient for a controlled circuit to operate. During the low effort retention mode the circuit module is supplied with a second voltage lower than the first voltage. The second voltage is sufficient for flop-flops to retain their state but not sufficient to guarantee proper circuit operation. The second voltage is produced by a voltage drop (droop) from the first voltage. The preferred embodiment includes a System On Chip and one external voltage regulator and an on-chip droop circuit for each circuit module.

Abstract translation: 电子电路的电源能够实现低功率保持模式。 在正常模式期间，向电路模块提供足以使受控电路工作的第一电压。 在低功耗保持模式期间，电路模块被提供有低于第一电压的第二电压。 第二个电压足以使电动机保持其状态，但不足以保证电路正常工作。 第二电压由第一电压的电压降（下降）产生。 优选实施例包括用于每个电路模块的片上系统和一个外部电压调节器和片上下降电路。

公开(公告)号：US08582384B1

公开(公告)日：2013-11-12

申请号：US13918276

申请日：2013-06-14

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet A. Chachad ,  Ramakrishnan Venkatasubramanian ,  Raguram Damodaran

IPC: G11C17/18

CPC classification number: G11C7/1039 ,  G11C7/22 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/0401 ,  G11C2029/0409

Abstract: In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.

公开(公告)号：US12259789B2

公开(公告)日：2025-03-25

申请号：US18239880

申请日：2023-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan Varadarajan ,  Ramakrishnan Venkatasubramanian ,  Varun Singh

IPC: G06F11/14 ,  H03M7/30

Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.

公开(公告)号：US20220413966A1

公开(公告)日：2022-12-29

申请号：US17901337

申请日：2022-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan Varadarajan ,  Ramakrishnan Venkatasubramanian ,  Varun Singh

IPC: G06F11/14 ,  H03M7/30

Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.

公开(公告)号：US20210208189A1

公开(公告)日：2021-07-08

申请号：US17127109

申请日：2020-12-18

Applicant: Texas Instruments Incorporated

Inventor： Jose Luis Flores ,  Ramakrishnan Venkatasubramanian ,  Samuel Paul Visalli

IPC: G01R31/28 ,  G06F1/3203 ,  G01R31/40

Abstract: In described examples, an SoC includes at least two voltage domains interconnected with a communication bus. Detection logic in a first voltage domain determines when a voltage error occurs in a second voltage domain and isolates communication via the communication bus when a voltage error or a timing error is detected.

公开(公告)号：US20190146790A1

公开(公告)日：2019-05-16

申请号：US16227238

申请日：2018-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00

Abstract: Disclosed embodiments include a data processing apparatus having a processing core, a memory, and a streaming engine. The streaming engine is configured to receive a plurality of data elements stored in the memory and to provide the plurality of data elements as a data stream to the processing core, and includes an address generator to generate addresses corresponding to locations in the memory, a buffer to store the data elements received from the locations in the memory corresponding to the generated addresses, and an output to supply the data elements received from the memory to the processing core as the data stream.

公开(公告)号：US10210090B1

公开(公告)日：2019-02-19

申请号：US15730893

申请日：2017-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/02 ,  G06F9/38 ,  G06F12/1027

Abstract: This invention involves a particular cache hazard. It is possible that an instruction request that is a miss in the cache occurs while the cache system is servicing a pending prefetch for the same instructions. In the prior art, this hazard is detected by comparing request addresses for all entries in a scoreboard. The program memory controller stores the allocated way in the scoreboard. The program memory controller compares the allocated way of the demand request to the allocated way of all the scoreboard entries. The cache hazard only occurs when the allocated ways match. Following way compare, the demand request address is compared to the request addresses of only those scoreboard entries having matching ways. Other address comparators are not powered during this time. This serves to reduce the electrical power required in detecting this cache hazard.

公开(公告)号：US09652402B2

公开(公告)日：2017-05-16

申请号：US14581487

申请日：2014-12-23

Applicant: Texas Instruments Incorporated

Inventor： Ramakrishnan Venkatasubramanian ,  Oluleye Olorode

IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/681 ,  G06F2212/684

Abstract: This invention hides the page miss translation latency for program fetches. In this invention whenever an access is requested by CPU that crosses a memory page boundary, the L1I cache controller request a next page translation along with the current page. This pipelines requests to the μTLB without waiting for L1I cache controller to begin processing the next page requests. This becomes a deterministic prefetch of the second page translation request. The translation information for the second page is stored locally in L1I cache controller and used when the access crosses the next page boundary.

公开(公告)号：US09557936B2

公开(公告)日：2017-01-31

申请号：US14587234

申请日：2014-12-31

Applicant: Texas Instruments Incorporated

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  David M. Thompson ,  Jonathan (Son) Hung Tran ,  Ramakrishnan Venkatasubramanian

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048

Abstract: This invention is data processing apparatus and method. Data is protecting from corruption using an error correction code by generating an error correction code corresponding to the data. In this invention the data and the corresponding error correction code are carried forward to another set of registers without regenerating the error correction code or using the error correction code for error detection or correction. Only later are error correction detection and correction actions taken. The differing data/error correction code registers may be in differing pipeline phases in the data processing apparatus. This invention forwards the error correction code with the data through the entire datapath that carries the data. This invention provides error protection to the whole datapath without requiring extensive hardware or additional time.

Abstract translation: 本发明是数据处理装置和方法。 通过产生对应于该数据的纠错码，使用纠错码来防止数据损坏。 在本发明中，将数据和相应的纠错码转发到另一组寄存器，而不用再生纠错码或使用纠错码进行错误检测或校正。 只有以后才采取纠错检测和纠正措施。 在数据处理装置中不同的数据/纠错码寄存器可能处于不同的流水线相位。 本发明通过携带数据的整个数据路径转发具有数据的纠错码。 本发明为整个数据路径提供错误保护，而不需要大量硬件或额外的时间。