公开(公告)号：US10205001B2

公开(公告)日：2019-02-12

申请号：US15226036

申请日：2016-08-02

Applicant: Texas Instruments Incorporated

Inventor： Sameer P. Pendharkar ,  John Lin

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08

Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

公开(公告)号：US20180108729A1

公开(公告)日：2018-04-19

申请号：US15843444

申请日：2017-12-15

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P. Pendharkar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/485 ,  H01L29/423

CPC classification number: H01L29/063 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

公开(公告)号：US20180097517A1

公开(公告)日：2018-04-05

申请号：US15809291

申请日：2017-11-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC: H03K17/687 ,  H01L27/092 ,  H01L29/06 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/7831 ,  H01L29/7835 ,  H03K17/122

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

公开(公告)号：US09633849B2

公开(公告)日：2017-04-25

申请号：US15093867

申请日：2016-04-08

Applicant: Texas Instruments Incorporated

Inventor： Sameer P. Pendharkar ,  Binghua Hu

IPC: H01L21/425 ,  H01L21/70 ,  H01L21/027 ,  H01L21/266 ,  H01L21/426 ,  H01L21/02 ,  H01L21/32 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/0274 ,  H01L21/02694 ,  H01L21/0271 ,  H01L21/266 ,  H01L21/32 ,  H01L21/426 ,  H01L21/823493 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist layer is developed (but not baked) to form a first resist geometry and a plurality of sublithographic resist geometries. The resist layer is baked causing the sublithographic resist geometries to reflow into a continuous second resist geometry having a thickness less that the first resist geometry. A high energy implant implants dopants through the second resist geometry but not through the first resist geometry. A low energy implant is blocked by both the first and second resist geometries.

公开(公告)号：US20160093612A1

公开(公告)日：2016-03-31

申请号：US14965182

申请日：2015-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/167 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L27/088 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7831

Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.